How to use cocotb - 10 common examples

@cocotb.test(expect_error=cocotb.triggers.TriggerException if cocotb.SIM_NAME.startswith(("xmsim", "ncsim")) and cocotb.LANGUAGE in ["vhdl"] else False)
def issue_120_scheduling(dut):

    cocotb.fork(Clock(dut.clk, 2500).start())
    cocotb.fork(monitor(dut))
    yield RisingEdge(dut.clk)

    # First attempt, not from coroutine - works as expected
    for i in range(2):
        dut.stream_in_valid = 1
        yield RisingEdge(dut.clk)
        dut.stream_in_valid = 0

    yield RisingEdge(dut.clk)

    # Failure - we don't drive valid on the rising edge even though
    # behaviour should be identical to the above

@cocotb.test(expect_error=cocotb.triggers.TriggerException if cocotb.SIM_NAME.startswith(("xmsim", "ncsim")) and cocotb.LANGUAGE in ["vhdl"] else False)
async def test_external_from_fork(dut):
    """
    Test that @external functions work when awaited from a forked
    task
    """
    async def run_function(dut):
        value = await external(calls_cocotb_function)(dut)
        return value

    async def run_external(dut):
        value = await external(return_two)(dut)
        return value

    clk_gen = cocotb.fork(Clock(dut.clk, 100, units='ns').start())

    coro1 = cocotb.fork(run_function(dut))

@cocotb.test(skip=cocotb.LANGUAGE in ["vhdl"])
async def test_access_underscore_name(dut):
    """Test accessing HDL name starting with an underscore"""
    # direct access does not work because we consider such names cocotb-internal
    with assert_raises(AttributeError):
        dut._underscore_name

    # indirect access works
    dut._id("_underscore_name", extended=False) <= 0
    await Timer(1, 'ns')
    assert dut._id("_underscore_name", extended=False).value == 0
    dut._id("_underscore_name", extended=False) <= 1
    await Timer(1, 'ns')
    assert dut._id("_underscore_name", extended=False).value == 1
    dut._id("_underscore_name", extended=False) <= 0
    await Timer(1, 'ns')
    assert dut._id("_underscore_name", extended=False).value == 0

@cocotb.test(skip=cocotb.SIM_NAME.lower().startswith(("icarus", "ghdl")))
async def test_ndim_array_handles(dut):
    """Test getting and setting multi-dimensional array values using the handle of the full array."""

    cocotb.fork(Clock(dut.clk, 1000, 'ns').start())

    # Set values with '<=' operator
    dut.array_2d <= [
        [0xF0, 0xE0, 0xD0, 0xC0],
        [0xB0, 0xA0, 0x90, 0x80]
    ]

    await Timer(1000, 'ns')

    _check_value(tlog, dut.array_2d, [[0xF0, 0xE0, 0xD0, 0xC0], [0xB0, 0xA0, 0x90, 0x80]])

    # Set values through HierarchyObject.__setattr__ method on 'dut' handle

@cocotb.test()
def test_coverage(dut):
    suite = unittest.TestSuite()
    suite.addTests(unittest.TestLoader().loadTestsFromModule(coverage_unittest))
    unittest.TextTestRunner().run(suite)
    yield Timer(1000)

@cocotb.test()
def test_discover_all(dut):
    r"""Discover everything in the DUT:
          dut
                 TYPE    CNT  NOTES                                                  EXCEPTIONS
             parameters: 7/2 (base types)                                            (VHDL/Verilog)
                           6 (param_rec.a, param_rec.b[0:2])                         (VHDL only excluding Aldec)
                          13 (param_cmplx[0:1].a, param_cmplx[0:1].b[0:2])           (VHDL only excluding Aldec)
                  ports:   1 (clk)
                           1 (select_in)                                             (VPI - Aldec sees as 32 bit register (i.e. cnt = 33)
                           9 (port_desc_in)
                           9 (port_asc_in)
                           9 (port_ofst_in)
                           9 (port_desc_out)
                           9 (port_asc_out)
                           9 (port_ofst_out)
                           1 (port_logic_out)

@cocotb.test()
def test_in_transfer(dut):
    harness = UsbTest(dut)
    yield harness.reset()
    yield harness.connect()

    addr = 28
    epaddr = EndpointType.epaddr(1, EndpointType.IN)
    yield harness.write(harness.csrs['usb_address'], addr)

    d = [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8]

    yield harness.clear_pending(epaddr)
    yield harness.set_response(epaddr, EndpointResponse.NAK)

    yield harness.set_data(epaddr, d[:4])
    yield harness.set_response(epaddr, EndpointResponse.ACK)

@cocotb.test(expect_fail=True)
def test_drivers(dut):
    """
    Try iterating over drivers of a signal.

    Seems that few simulators implement vpiDriver
    """
    tlog = logging.getLogger("cocotb.test")
    yield Timer(100)
    for driver in dut.i_verilog.uart1.uart_rx_1.rx_data.drivers():
        tlog.info("Found %s" % repr(driver))
        break
    else:
        raise TestFailure("No drivers found for dut.i_verilog.uart1.uart_rx_1.rx_data")

@cocotb.test(skip=cocotb.SIM_NAME in ["Icarus Verilog"])
def issue_330_direct(dut):
    """
    Access a structure
    """

    tlog = logging.getLogger("cocotb.test")
    yield Timer(10)

    structure = dut.inout_if

    tlog.info("Value of inout_if => a_in = %s ; b_out = %s" % (structure.a_in, structure.b_out))

@cocotb.test()
def test_debug_out(dut):
    harness = UsbTest(dut)
    yield harness.reset()
    yield harness.connect()

    addr = 0
    yield harness.write(harness.csrs['usb_address'], addr)
    reg_addr = harness.csrs['ctrl_scratch']
    setup_data = [0x43, 0x00,
                    (reg_addr >> 0) & 0xff,
                    (reg_addr >> 8) & 0xff,
                    (reg_addr >> 16) & 0xff,
                    (reg_addr >> 24) & 0xff, 0x04, 0x00]
    ep0in_addr = EndpointType.epaddr(0, EndpointType.IN)
    ep1in_addr = EndpointType.epaddr(1, EndpointType.IN)
    ep0out_addr = EndpointType.epaddr(0, EndpointType.OUT)