How to use the cocotb.SIM_NAME function in cocotb

@cocotb.test(expect_error=cocotb.triggers.TriggerException if cocotb.SIM_NAME.startswith(("xmsim", "ncsim")) and cocotb.LANGUAGE in ["vhdl"] else False)
def issue_120_scheduling(dut):

    cocotb.fork(Clock(dut.clk, 2500).start())
    cocotb.fork(monitor(dut))
    yield RisingEdge(dut.clk)

    # First attempt, not from coroutine - works as expected
    for i in range(2):
        dut.stream_in_valid = 1
        yield RisingEdge(dut.clk)
        dut.stream_in_valid = 0

    yield RisingEdge(dut.clk)

    # Failure - we don't drive valid on the rising edge even though
    # behaviour should be identical to the above

@cocotb.test(expect_error=cocotb.SIM_NAME in ["Icarus Verilog"])
def test_integer(dut):
    """
    Test access to integers
    """
    log = logging.getLogger("cocotb.test")
    yield Timer(10)
    dut.stream_in_int = 4
    yield Timer(10)
    yield Timer(10)
    got_in = int(dut.stream_out_int)
    got_out = int(dut.stream_in_int)
    log.info("dut.stream_out_int = %d" % got_out)
    log.info("dut.stream_in_int = %d" % got_in)
    if got_in != got_out:
        raise TestFailure("stream_in_int and stream_out_int should not match")

@cocotb.test(expect_error=cocotb.triggers.TriggerException if cocotb.SIM_NAME.startswith(("xmsim", "ncsim")) and cocotb.LANGUAGE in ["vhdl"] else False)
def issue_348_rising(dut):
    """ Start two monitors on RisingEdge """
    yield DualMonitor(RisingEdge, dut.clk).start()

@cocotb.test(expect_error=cocotb.SIM_NAME in ["Icarus Verilog"])
def assign_double(dut):
    """
    Assign a random floating point value, read it back from the DUT and check
    it matches what we assigned
    """
    val = random.uniform(-1e307, 1e307)
    log = logging.getLogger("cocotb.test")
    yield Timer(1)
    log.info("Setting the value %g" % val)
    dut.stream_in_real = val
    yield Timer(1)
    yield Timer(1)  # FIXME: Workaround for VHPI scheduling - needs investigation
    got = float(dut.stream_out_real)
    log.info("Read back value %g" % got)
    if got != val:
        raise TestFailure("Values didn't match!")

@cocotb.test(expect_fail=cocotb.SIM_NAME in ["Icarus Verilog"])
def recursive_discovery(dut):
    """
    Recursively discover every single object in the design
    """
    if cocotb.SIM_NAME.lower().startswith(("modelsim",
                                           "ncsim",
                                           "xmsim",
                                           "chronologic simulation vcs")):
        # vpiAlways does not show up
        pass_total = 259
    else:
        pass_total = 265

    tlog = logging.getLogger("cocotb.test")
    yield Timer(100)

@cocotb.test(expect_error=cocotb.SIM_NAME in ["Icarus Verilog"])
def test_real_assign_int(dut):
    """Assign a random integer value to ensure we can write types convertible to
    int, read it back from the DUT and check it matches what we assigned.
    """
    val = random.randint(-2**31, 2**31 - 1)
    log = logging.getLogger("cocotb.test")
    yield Timer(1)
    log.info("Setting the value %i" % val)
    dut.stream_in_real <= val
    yield Timer(1)
    yield Timer(1)  # FIXME: Workaround for VHPI scheduling - needs investigation
    got = dut.stream_out_real
    log.info("Read back value %d" % got)
    if got != float(val):
        raise TestFailure("Values didn't match!")

@cocotb.test(expect_error=cocotb.triggers.TriggerException if cocotb.SIM_NAME.startswith(("xmsim", "ncsim")) and cocotb.LANGUAGE in ["vhdl"] else False)
def issue_142_overflow_error(dut):
    """Tranparently convert ints too long to pass
       through the GPI interface natively into BinaryValues"""
    cocotb.fork(Clock(dut.clk, 2500).start())

    def _compare(value):
        if int(dut.stream_in_data_wide.value) != int(value):
            raise TestFailure("Expecting 0x%x but got 0x%x on %s" % (
                int(value), int(dut.stream_in_data_wide.value),
                str(dut.stream_in_data_wide)))

    # Wider values are transparently converted to BinaryValues
    for value in [0, 0x7FFFFFFF, 0x7FFFFFFFFFFF, BinaryValue(0x7FFFFFFFFFFFFF,len(dut.stream_in_data_wide),bigEndian=False)]:

        dut.stream_in_data_wide <= value
        yield RisingEdge(dut.clk)

cocotb.fork(Clock(dut.clk, 1000).start())

    yield Timer(1000)

    tlog.info("Checking Generics/Parameters:")
    _check_logic(tlog, dut.param_logic    , 1)
    _check_logic(tlog, dut.param_logic_vec, 0xDA)

    if cocotb.LANGUAGE in ["vhdl"]:
        _check_int(tlog, dut.param_bool, 1)
        _check_int(tlog, dut.param_int , 6)
        _check_real(tlog, dut.param_real, 3.14)
        _check_int(tlog, dut.param_char, ord('p'))
        _check_str(tlog, dut.param_str , b"ARRAYMOD")

        if not cocotb.SIM_NAME.lower().startswith(("riviera")):
            _check_logic(tlog, dut.param_rec.a        , 0)
            _check_logic(tlog, dut.param_rec.b[0]     , 0)
            _check_logic(tlog, dut.param_rec.b[1]     , 0)
            _check_logic(tlog, dut.param_rec.b[2]     , 0)
            _check_logic(tlog, dut.param_cmplx[0].a   , 0)
            _check_logic(tlog, dut.param_cmplx[0].b[0], 0)
            _check_logic(tlog, dut.param_cmplx[0].b[1], 0)
            _check_logic(tlog, dut.param_cmplx[0].b[2], 0)
            _check_logic(tlog, dut.param_cmplx[1].a   , 0)
            _check_logic(tlog, dut.param_cmplx[1].b[0], 0)
            _check_logic(tlog, dut.param_cmplx[1].b[1], 0)
            _check_logic(tlog, dut.param_cmplx[1].b[2], 0)

    tlog.info("Checking Constants:")
    _check_logic(tlog, dut.const_logic    , 0)
    _check_logic(tlog, dut.const_logic_vec, 0x3D)

    expect_error=cocotb.SIM_NAME.lower().startswith("modelsim")  # $fatal() fails hard on Questa
)
async def test_failure_from_system_task(dut):
    """
    Allow the dut to call system tasks from verilog.
    $fatal() will fail the test, and scheduler will cleanup forked coroutines.
    """
    cocotb.fork(Clock(dut.clk, 100, units='ns').start())
    cocotb.fork(clock_mon(dut))
    cocotb.fork(run_external(dut))
    await Timer(10000000, units='ns')