How to use the cocotb.decorators.coroutine function in cocotb

@coroutine
def waiting_coroutine(some_event):
    some_event.log.info("Putting waiting coroutine to sleep until this event fires")
    yield some_event.wait()
    some_event.log.info("Coroutine woke up again!  Awesome")

    @coroutine
    def _send_thread(self):
        while True:

            # Sleep until we have something to send
            while not self._sendQ:
                self._pending.clear()
                yield self._pending.wait()

            synchronised = False

            # Send in all the queued packets,
            # only synchronize on the first send
            while self._sendQ:
                transaction, callback, event, kwargs = self._sendQ.popleft()
                self.log.debug("Sending queued packet...")
                yield self._send(transaction, callback, event,

@coroutine
def clock_monitor(signal, output):
    while True:
        yield Edge(signal)
        signal.log.info("Edge triggered:  %s : %s = %s" % (signal.getvalue().value, str(output), output.getvalue().value))

    @coroutine 
    def _clk_cycle_counter(self):
        """
        """
        clkedge = RisingEdge(self.clock)
        self._clk_cycle_count = 0
        while True:
            if self._cycle:
                self._clk_cycle_count += 1
            else:
                self._clk_cycle_count = 0
            yield clkedge

    @coroutine
    def _driver_send(self, value, sync=True):
        """Send a transmission over the bus.

        Args:
            value: data to drive onto the bus.
        """
        self.log.debug("Sending Avalon transmission: %r", value)

        # Avoid spurious object creation by recycling
        clkedge = RisingEdge(self.clock)

        word = BinaryValue(n_bits=len(self.bus.data), bigEndian=False)

        # Drive some defaults since we don't know what state we're in
        self.bus.valid <= 0

@coroutine
def reset_dut(clock, reset, enable):
    clock_ticks = 0
    reset <= 1
    enable <= 0
    while True:
        yield Edge(clock)
        clock_ticks += 1
        if clock_ticks >= 4:
            reset <= 0
            enable <= 1
            break
    reset.log.info("Released reset: %s" % reset.getvalue())

    @coroutine
    def _wait_stall(self):
        """Wait for stall to be low before continuing (Pipelined Wishbone)
        """
        clkedge = RisingEdge(self.clock)
        count = 0
        if hasattr(self.bus, "stall"):
            count = 0            
            while self.bus.stall.getvalue():
                yield clkedge
                count += 1
                if (not (self._timeout is None)):
                    if (count > self._timeout): 
                        raise TestFailure("Timeout of %u clock cycles reached when on stall from slave" % self._timeout)                
            self.log.debug("Stalled for %u cycles" % count)
        raise ReturnValue(count)

    @coroutine
    def _close_cycle(self):
        #Close current wishbone cycle  
        clkedge = RisingEdge(self.clock)
        count           = 0
        last_acked_ops  = 0
        #Wait for all Operations being acknowledged by the slave before lowering the cycle line
        #This is not mandatory by the bus standard, but a crossbar might send acks to the wrong master
        #if we don't wait. We don't want to risk that, it could hang the bus
        while self._acked_ops < self._op_cnt:
            if last_acked_ops != self._acked_ops:
                self.log.debug("Waiting for missing acks: %u/%u" % (self._acked_ops, self._op_cnt) )
            last_acked_ops = self._acked_ops    
            #check for timeout when finishing the cycle            
            count += 1
            if (not (self._timeout is None)):
                if (count > self._timeout):

    @coroutine
    def _writing_byte_value(self, byteaddr):
        """Writing value in _mem with byteaddr size."""
        yield FallingEdge(self.clock)
        for i in range(self.dataByteSize):
            data = self.bus.writedata.value.integer
            addrtmp = byteaddr + i
            datatmp = (data >> (i*8)) & 0xff
            self._mem[addrtmp] = datatmp

@coroutine
def driver(clock, ready, data):
    """Drives incrementing values onto a bus each time ready is high"""
    data <= 0
    while True:
        yield RisingEdge(ready)
        data <= data.value.value + 1