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def do_single_edge_check(dut, level):
"""Do test for rising edge"""
old_value = dut.clk.value.integer
dut._log.info("Value of %s is %d" % (dut.clk._path, old_value))
if old_value is level:
raise TestError("%s not to %d start with" % (dut.clk._path, not level))
if level == 1:
yield RisingEdge(dut.clk)
else:
yield FallingEdge(dut.clk)
new_value = dut.clk.value.integer
dut._log.info("Value of %s is %d" % (dut.clk._path, new_value))
if new_value is not level:
raise TestError("%s not %d at end" % (dut.clk._path, level))
if not isinstance(asc_gen_20, HierarchyObject):
raise TestFailure("Generate Loop child >{!r}< should be HierarchyObject".format(asc_gen_20))
tlog.info("Direct access found %s", asc_gen_20)
tlog.info("Direct access found %s", desc_gen)
for gens in desc_gen:
tlog.info("Iterate access found %s", gens)
if len(desc_gen) != 8:
raise TestError("Length of desc_gen is >{}< and should be 8".format(len(desc_gen)))
else:
tlog.info("Length of desc_gen is %d", len(desc_gen))
if len(dut.asc_gen) != 8:
raise TestError("Length of asc_gen is >{}< and should be 8".format(len(dut.asc_gen)))
else:
tlog.info("Length of asc_gen is %d", len(dut.asc_gen))
for gens in dut.asc_gen:
tlog.info("Iterate access found %s", gens)
def do_single_edge_check(dut, level):
"""Do test for rising edge"""
old_value = dut.clk.value.integer
dut._log.info("Value of %s is %d" % (dut.clk._path, old_value))
if old_value is level:
raise TestError("%s not to %d start with" % (dut.clk._path, not level))
if level == 1:
yield RisingEdge(dut.clk)
else:
yield FallingEdge(dut.clk)
new_value = dut.clk.value.integer
dut._log.info("Value of %s is %d" % (dut.clk._path, new_value))
if new_value is not level:
raise TestError("%s not %d at end" % (dut.clk._path, level))
def write(self, address: int, value: int) -> None:
"""Issue a write to the given address with the specified
value.
Args:
address: The address to write to.
value: The data value to write.
Raises:
:any:`TestError`: If master is read-only.
"""
if not self._can_write:
self.log.error("Cannot write - have no write signal")
raise TestError("Attempt to write on a read-only AvalonMaster")
yield self._acquire_lock()
# Apply values to bus
yield RisingEdge(self.clock)
self.bus.address <= address
self.bus.writedata <= value
self.bus.write <= 1
if hasattr(self.bus, "byteenable"):
self.bus.byteenable <= int("1"*len(self.bus.byteenable), 2)
if hasattr(self.bus, "cs"):
self.bus.cs <= 1
# Wait for waitrequest to be low
if hasattr(self.bus, "waitrequest"):
yield self._wait_for_nsignal(self.bus.waitrequest)
for _ in range(self.off):
yield clkedge
# Grab the next set of on/off values
self._next_valids()
# Consume a valid cycle
if self.on is not True and self.on:
self.on -= 1
self.bus.valid <= 1
if hasattr(self.bus, 'channel'):
if channel is None:
self.bus.channel <= 0
elif channel > self.config['maxChannel'] or channel < 0:
raise TestError("%s: Channel value %d is outside range 0-%d" %
(self.name, channel, self.config['maxChannel']))
else:
self.bus.channel <= channel
if firstword:
self.bus.startofpacket <= 1
firstword = False
else:
self.bus.startofpacket <= 0
nbytes = min(len(string), bus_width)
data = string[:nbytes]
word.buff = data
if len(string) <= bus_width:
self.bus.endofpacket <= 1
t = handle.get_type()
# Special case for constants
if handle.get_const() and t not in [
simulator.MODULE,
simulator.STRUCTURE,
simulator.NETARRAY,
simulator.GENARRAY,
]:
obj = ConstantObject(handle, path, t)
_handle2obj[handle] = obj
return obj
if t not in _type2cls:
raise TestError("Couldn't find a matching object for GPI type %d (path=%s)" % (t, path))
obj = _type2cls[t](handle, path)
_handle2obj[handle] = obj
return obj
but syntactically it blocks.
Args:
address: The address to read from.
sync: Wait for rising edge on clock initially.
Defaults to True.
Returns:
The read data value.
Raises:
:any:`TestError`: If master is write-only.
"""
if not self._can_read:
self.log.error("Cannot read - have no read signal")
raise TestError("Attempt to read on a write-only AvalonMaster")
yield self._acquire_lock()
# Apply values for next clock edge
if sync:
yield RisingEdge(self.clock)
self.bus.address <= address
self.bus.read <= 1
if hasattr(self.bus, "byteenable"):
self.bus.byteenable <= int("1"*len(self.bus.byteenable), 2)
if hasattr(self.bus, "cs"):
self.bus.cs <= 1
# Wait for waitrequest to be low
if hasattr(self.bus, "waitrequest"):
yield self._wait_for_nsignal(self.bus.waitrequest)
if self.use_empty:
empty = BinaryValue(n_bits=len(self.bus.empty), bigEndian=False)
# Drive some defaults since we don't know what state we're in
if self.use_empty:
self.bus.empty <= 0
self.bus.startofpacket <= 0
self.bus.endofpacket <= 0
self.bus.valid <= 0
if hasattr(self.bus, 'error'):
self.bus.error <= 0
if hasattr(self.bus, 'channel'):
self.bus.channel <= 0
elif channel is not None:
raise TestError("%s does not have a channel signal" % self.name)
while string:
if not firstword or (firstword and sync):
yield clkedge
# Insert a gap where valid is low
if not self.on:
self.bus.valid <= 0
for _ in range(self.off):
yield clkedge
# Grab the next set of on/off values
self._next_valids()
# Consume a valid cycle
if self.on is not True and self.on:
Use ``TestError(msg)`` directly instead of this function.
Args:
obj: Object with a log method.
msg (str): The log message.
"""
warnings.warn(
"``create_error`` is deprecated - use ``TestError(msg)`` directly "
"(or any other exception type) instead",
DeprecationWarning, stacklevel=2)
try:
# use the private version to avoid multiple warnings
_raise_error(obj, msg)
except TestError as error:
return error
return TestError("Creating error traceback failed")
if hasattr(self.bus, "readdata"):
self._width = len(self.bus.readdata)
self.dataByteSize = int(self._width/8)
self._readable = True
if hasattr(self.bus, "writedata"):
width = len(self.bus.writedata)
if (self._width is not None) and self._width != width:
self.log.error("readdata and writedata bus" +
" are not the same size")
self._width = width
self.dataByteSize = int(self._width/8)
self._writeable = True
if not self._readable and not self._writeable:
raise TestError("Attempt to instantiate useless memory")
# Allow dual port RAMs by referencing the same dictionary
if memory is None:
self._mem = {}
else:
self._mem = memory
self._val = BinaryValue(n_bits=self._width, bigEndian=False)
self._readlatency_min = readlatency_min
self._readlatency_max = readlatency_max
self._responses = []
self._coro = cocotb.fork(self._respond())
if hasattr(self.bus, "readdatavalid"):
self.bus.readdatavalid.setimmediatevalue(0)