How to use the cocotb.triggers.RisingEdge function in cocotb

def simple_wb_test(dut):
    cocotb.fork(Clock(dut.wb_clk_i, 1000).start())

    for i in range(100):
        yield RisingEdge(dut.wb_clk_i)

def monitor(dut):
    for i in range(4):
        yield RisingEdge(dut.clk)
    yield ReadOnly()
    if not dut.stream_in_valid.value.integer:
        raise TestFailure("stream_in_valid should be high on the 5th cycle")

async def clock_monitor(dut):
        count = 0
        while True:
            await RisingEdge(dut.clk)
            await Timer(1000, units='ns')
            count += 1

def wait_for(clk, cycles):
        rising_edge = RisingEdge(clk)
        for _ in range(cycles):
            yield rising_edge
        return 3

self.rx_frame_asserted = False
                    self.dut.rx_frame_in_p <= 0
                    self.dut.rx_frame_in_n <= 1
                else:
                    if index < len(i_data):
                        i_bin_val.set_value(i_data[index])
                        q_bin_val.set_value(q_data[index])
                        index += 1
                    else:
                        return
                    self.dut.rx_data_in_p <= i_bin_val[11:6]
                    self.dut.rx_data_in_n <= ~i_bin_val[11:6]
                    self.rx_frame_asserted = True
                    self.dut.rx_frame_in_p <= 1
                    self.dut.rx_frame_in_n <= 0
                yield RisingEdge(self.dut.rx_clk_in_n)
                if self.rx_frame_asserted:
                    self.dut.rx_data_in_p <= q_bin_val[11:6]
                    self.dut.rx_data_in_n <= ~q_bin_val[11:6]
                else:
                    self.dut.rx_data_in_p <= q_bin_val[5:0]
                    self.dut.rx_data_in_n <= ~q_bin_val[5:0]
        else:
            I_SEND_HIGH = True
            Q_SEND_HIGH = True
            channel = 1
            while True:
                yield RisingEdge(self.dut.rx_clk_in_p)
                if I_SEND_HIGH:
                    self.dut.rx_data_in_p <= i_bin_val[11:6]
                    self.dut.rx_data_in_n <= ~i_bin_val[11:6]
                    I_SEND_HIGH = False

def _cr_twiddler(self, generator=None):
        if generator is None and self._generator is None:
            raise Exception("No generator provided!")
        if generator is not None:
            self._generator = generator

        edge = RisingEdge(self._clk)

        # Actual thread
        while True:
            on, off = next(self._generator)
            self._signal <= 1
            for _ in range(on):
                yield edge
            self._signal <= 0
            for _ in range(off):
                yield edge

def _wait_ack(self):
        """Wait for ACK on the bus before continuing (Non pipelined Wishbone)
        """
        #wait for acknownledgement before continuing - Classic Wishbone without pipelining
        clkedge = RisingEdge(self.clock)
        count = 0
        if not hasattr(self.bus, "stall"):
            while not self._get_reply():
                yield clkedge
                count += 1
            self.log.debug("Waited %u cycles for ackknowledge" % count)
        raise ReturnValue(count)

delay=data_latency))

        if c_addr:
            yield c_addr.join()
        if c_data:
            yield c_data.join()

        # Wait for the response
        while True:
            yield ReadOnly()
            if self.bus.BVALID.value and self.bus.BREADY.value:
                result = self.bus.BRESP.value
                break
            yield RisingEdge(self.clock)

        yield RisingEdge(self.clock)

        if int(result):
            raise AXIProtocolError("Write to address 0x%08x failed with BRESP: %d"
                                   % (address, int(result)))

        return result

def _send_write_data(self, data, delay=0, byte_enable=0xF):
        """Send the write address, with optional delay (in clocks)."""
        yield self.write_data_busy.acquire()
        for cycle in range(delay):
            yield RisingEdge(self.clock)

        self.bus.WDATA <= data
        self.bus.WVALID <= 1
        self.bus.WSTRB <= byte_enable

        while True:
            yield ReadOnly()
            if self.bus.WREADY.value:
                break
            yield RisingEdge(self.clock)
        yield RisingEdge(self.clock)
        self.bus.WVALID <= 0
        self.write_data_busy.release()

def _tx_data_from_ad9361(self):
        i_bin_val = BinaryValue(n_bits=12, bigEndian=False)
        q_bin_val = BinaryValue(n_bits=12, bigEndian=False)
        while True:
            yield RisingEdge(self.dut.tx_clk_out_p)
            if self.dut.tx_frame_out_p.value.integer == 1:
                q_bin_val[11:6] = self.dut.tx_data_out_p.value.get_binstr()
            else:
                q_bin_val[5:0] = self.dut.tx_data_out_p.value.get_binstr()
            yield RisingEdge(self.dut.tx_clk_out_n)
            if self.dut.tx_frame_out_p.value.integer == 1:
                i_bin_val[11:6] = self.dut.tx_data_out_p.value.get_binstr()
            else:
                i_bin_val[5:0] = self.dut.tx_data_out_p.value.get_binstr()
                # print("i_data",i_bin_val.get_value())
                # print("q_data",q_bin_val.get_value())
                self.lbqi.append(i_bin_val)
                self.lbqq.append(q_bin_val)
                self.got_tx.set([i_bin_val, q_bin_val])