How to use the cocotb.result.ReturnValue function in cocotb

% (DiPacket.TYPE_SUB.RESP_WRITE_REG_SUCCESS.name,
                       DiPacket.TYPE_SUB(rx_packet.type_sub).name))

            self.dut._log.debug("Successfully wrote %d bit register 0x%04x of "
                                "module at DI address 0x%04x."
                                % (word_width, regaddr, dest))
            success = True

        except RegAccessFailedException as reg_acc_error:
            if fatal_errors:
                raise TestFailure(reg_acc_error.message)
            else:
                self.dut._log.info(reg_acc_error.message)
                success = False

        raise ReturnValue(success)

def read(self, addr):
        value = yield self.wb.read(addr)
        raise ReturnValue(value)

if wait_time >= self.read_timeout_cycles:
                self.log.warning("packet receive timed out after %d idle cycles"
                                 % self.read_timeout_cycles)
                raise ReturnValue(None)

            yield RisingEdge(self.clock)

        if set_ready:
            self.bus.debug_out_ready <= 0

        pkg = DiPacket()
        pkg.flits = flits

        self.log.debug("Received packet " + str(pkg))

        raise ReturnValue(pkg)

def get_value():
        yield cocotb.triggers.Timer(1, units='ns')
        raise cocotb.result.ReturnValue(42)

def _wait_ack(self):
        """Wait for ACK on the bus before continuing (Non pipelined Wishbone)
        """
        #wait for acknownledgement before continuing - Classic Wishbone without pipelining
        clkedge = RisingEdge(self.clock)
        count = 0
        if not hasattr(self.bus, "stall"):
            while not self._get_reply():
                yield clkedge
                count += 1
            self.log.debug("Waited %u cycles for ackknowledge" % count)
        raise ReturnValue(count)    

self.dut.log.error("Timed out while waiting for master to be respond")
                return

            data_index += 1
            #yield RisingEdge(self.dut.clk)
            #yield ReadOnly()
            value = self.out_data.value.get_value()
            print "%d Received: 0x%08X" % (data_index, value)
            self.response.append(0xFF & (value >> 24))
            self.response.append(0xFF & (value >> 16))
            self.response.append(0xFF & (value >> 8))
            self.response.append(0xFF & value)

        self.out_ready      <= 0
 
        raise ReturnValue(self.response)

yield self._close_cycle()

                #do pick and mix from result- and auxiliary buffer so we get all operation and meta info
                for res, aux in zip(self._res_buf, self._aux_buf):
                    res.datwr       = aux.datwr
                    res.sel         = aux.sel
                    res.adr         = aux.adr
                    res.waitIdle    = aux.waitIdle
                    res.waitStall   = aux.waitStall
                    res.waitAck    -= aux.ts
                    result.append(res)

            raise ReturnValue(result)
        else:
            raise TestFailure("Sorry, argument must be a list of WBOp (Wishbone Operation) objects!")
            raise ReturnValue(None)

self.bus.PENABLE <= 1
        while True:
            yield ReadOnly()
            if (self.bus.PREADY == 1):
                rval = self.bus.PRDATA
                break
            yield RisingEdge(self.clock)
        yield RisingEdge(self.clock)
        self.bus.PADDR <= 0
        self.bus.PWDATA <= 0
        self.bus.PSELx <= 0
        self.bus.PWRITE <= 0
        self.bus.PENABLE <= 0
        for i in range(transaction.delay):
            yield RisingEdge(self.clock)
        raise ReturnValue(rval)

timeout_count           =  0
            data_index              += 1
            value = self.dut.out_data.value.get_value()
            self.response.append(0xFF & (value >> 24))
            self.response.append(0xFF & (value >> 16))
            self.response.append(0xFF & (value >> 8))
            self.response.append(0xFF & value)
            yield( self.wait_clocks(1))
            self.dut.out_ready      <= 1

        if self.dut.master_ready.value.get_value() == 0:
            yield RisingEdge(self.dut.master_ready)

        yield( self.wait_clocks(10))
        self.comm_lock.release()
        raise ReturnValue(self.response)