How to use skidl - 10 common examples

To help you get started, we’ve selected a few skidl examples, based on popular ways it is used in public projects.

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github xesscorp / skidl / skidl / Net.py View on Github external
return nets[1]
                if fixed0 and fixed1:
                    log_and_raise(
                        logger,
                        ValueError,
                        "Cannot merge two nets with fixed names: {} and {}.".format(
                            name0, name1
                        ),
                    )
                if nets[1].is_implicit():

                    return nets[0]
                if nets[0].is_implicit():
                    return nets[1]
                if name0 != name1:
                    logger.warning(
                        "Merging two named nets ({name0} and {name1}) into {name0}.".format(
                            **locals()
                        )
                    )
                return nets[0]

            # More than two nets, so bisect the list into two smaller lists and
            # recursively find the best name from each list and then return the
            # best name of those two.
            mid_point = len(nets) // 2
            return select_name(
                [select_name(nets[0:mid_point]), select_name(nets[mid_point:])]
            )
github xesscorp / skidl / skidl / tools / spice.py View on Github external
# Create the part with the part definition.
            part = _mk_subckt_part(line)  # Create un-filled part template.

            # Flesh-out the part.
            part.filename = filepath  # Store filename where this part came from.

            # Parse the part definition.
            pieces = part.part_defn.split()
            try:
                # part defn: .subckt part_name pin1, pin2, ... pinN.
                part.name = pieces[1]
                part.pins = [Pin(num=p, name=p) for p in pieces[2:]]
                part.associate_pins()
            except IndexError:
                logger.warn("Misformatted SPICE subcircuit: {}".format(part.part_defn))
            else:
                # Now find a symbol file for the part to assign names to the pins.
                # First, check for LTSpice symbol file.
                sym_file, _ = find_and_open_file(
                    part.name,
                    lib_search_paths_,
                    ".asy",
                    allow_failure=True,
                    exclude_binary=True,
                    descend=-1,
                )
                if sym_file:
                    pin_names = []
                    pin_indices = []
                    for sym_line in sym_file:
                        if sym_line.lower().startswith("pinattr pinname"):
github xesscorp / skidl / skidl / Part.py View on Github external
ios = ",".join(io).split(INDEX_SEPARATOR)

        # Add a pin to the part for each pin name.
        for i, arg in enumerate(ios):
            arg = arg.strip()  # Strip any spaces that may have been between pin names.

            # If [pin_name] or pin_name[], then add a PinList to the part. Don't use
            # part.add_pins() because it will flatten the PinList and add nothing since
            # the PinList is empty.
            if arg[0] + arg[-1] == "[]":
                self.pins.append(PinList(num=i, name=arg[1:-1], part=self))
            elif arg[-2:] == "[]":
                self.pins.append(PinList(num=i, name=arg[0:-2], part=self))
            else:
                # Add a simple, non-vector pin.
                self.add_pins(Pin(num=i, name=arg))
github xesscorp / skidl / skidl / skidl.py View on Github external
builtins.default_circuit = Circuit()
# NOCONNECT net for attaching pins that are intentionally left open.
builtins.NC = default_circuit.NC  # pylint: disable=undefined-variable

# Create calls to functions on whichever Circuit object is the current default.
ERC = default_circuit.ERC  # pylint: disable=undefined-variable
generate_netlist = (
    default_circuit.generate_netlist
)  # pylint: disable=undefined-variable
generate_xml = default_circuit.generate_xml  # pylint: disable=undefined-variable
generate_graph = default_circuit.generate_graph  # pylint: disable=undefined-variable
reset = default_circuit.reset  # pylint: disable=undefined-variable
backup_parts = default_circuit.backup_parts  # pylint: disable=undefined-variable

# Define a tag for nets that convey power (e.g., VCC or GND).
POWER = Pin.drives.POWER


def no_files(circuit=default_circuit):
    """Prevent creation of output files (netlists, ERC, logs) by this Circuit object."""
    circuit.no_files = True
    erc_logger.stop_file_output()
    logger.stop_file_output()
github xesscorp / skidl / skidl / libs / references_sklib.py View on Github external
from skidl import SKIDL, TEMPLATE, Part, Pin, SchLib

SKIDL_lib_version = '0.0.1'

references = SchLib(tool=SKIDL).add_parts(*[
        Part(name='CJ432',dest=TEMPLATE,tool=SKIDL,keywords='diode device shunt regulator',description='Shunt Regulator, SOT-23',ref_prefix='D',num_units=1,fplist=['SOT*23*'],do_erc=True,pins=[
            Pin(num='1',name='REF',func=Pin.PASSIVE,do_erc=True),
            Pin(num='2',name='K',func=Pin.PASSIVE,do_erc=True),
            Pin(num='3',name='A',func=Pin.PASSIVE,do_erc=True)]),
        Part(name='ISL21070DIH306Z-TK',dest=TEMPLATE,tool=SKIDL,keywords='Micropower Voltage Reference 0.6V',description='ISL201070 Series, 0.6V 25μA Micropower Voltage Reference, SOT-23',ref_prefix='U',num_units=1,fplist=['SOT-23*'],do_erc=True,aliases=['ISL21070CIH320Z-TK', 'ISL21070CIH325Z-TK'],pins=[
            Pin(num='1',name='Vin',func=Pin.PWRIN,do_erc=True),
            Pin(num='2',name='Vout',func=Pin.PASSIVE,do_erc=True),
            Pin(num='3',name='GND',func=Pin.PWRIN,do_erc=True)]),
        Part(name='LM134H/NOPB',dest=TEMPLATE,tool=SKIDL,keywords='Adjustable Current Source 10mA',description='LM134H, 1μA to 10mA 3-Terminal Adjustable Current Source, TO-46',ref_prefix='U',num_units=1,fplist=['TO?46*'],do_erc=True,pins=[
            Pin(num='1',name='~',func=Pin.PASSIVE,do_erc=True),
            Pin(num='2',name='~',func=Pin.PASSIVE,do_erc=True),
            Pin(num='3',name='~',func=Pin.PASSIVE,do_erc=True)]),
        Part(name='LM285D-1.2',dest=TEMPLATE,tool=SKIDL,keywords='diode device voltage reference',description='2.500V Micropower Voltage Reference Diodes, SO-8',ref_prefix='D',num_units=1,fplist=['SOIC*3.9x4.9m*_Pitch1.27mm*'],do_erc=True,aliases=['LM285D-2.5', 'LM385D-1.2', 'LM385D-2.5'],pins=[
            Pin(num='1',name='NC',func=Pin.NOCONNECT,do_erc=True),
            Pin(num='2',name='NC',func=Pin.NOCONNECT,do_erc=True),
            Pin(num='3',name='NC',func=Pin.NOCONNECT,do_erc=True),
            Pin(num='4',name='A',func=Pin.PASSIVE,do_erc=True),
            Pin(num='5',name='NC',func=Pin.NOCONNECT,do_erc=True),
github xesscorp / skidl / skidl / libs / battery_management_sklib.py View on Github external
Pin(num='15',name='DACV',do_erc=True),
            Pin(num='16',name='PGND',func=Pin.PWRIN,do_erc=True),
            Pin(num='17',name='DrvLO',func=Pin.OUTPUT,do_erc=True),
            Pin(num='18',name='DrvHI',func=Pin.OUTPUT,do_erc=True),
            Pin(num='19',name='LX',do_erc=True)]),
        Part(name='MAX1648',dest=TEMPLATE,tool=SKIDL,keywords='battery charger',description='Smart Battery Charger, 18V battery, 28V input, standalone',ref_prefix='U',num_units=1,do_erc=True,pins=[
            Pin(num='1',name='DCIN',do_erc=True),
            Pin(num='2',name='VLout',func=Pin.OUTPUT,do_erc=True),
            Pin(num='3',name='CCV',do_erc=True),
            Pin(num='4',name='CCI',do_erc=True),
            Pin(num='5',name='CurrSense',do_erc=True),
            Pin(num='6',name='BATT',do_erc=True),
            Pin(num='7',name='REF',func=Pin.BIDIR,do_erc=True),
            Pin(num='8',name='AGND',func=Pin.PWRIN,do_erc=True),
            Pin(num='9',name='THM',do_erc=True),
            Pin(num='10',name='SETI',func=Pin.OPENCOLL,do_erc=True),
            Pin(num='11',name='SETV',do_erc=True),
            Pin(num='12',name='PGND',func=Pin.PWRIN,do_erc=True),
            Pin(num='13',name='DrvLO',func=Pin.OUTPUT,do_erc=True),
            Pin(num='14',name='DrvHI',func=Pin.OUTPUT,do_erc=True),
            Pin(num='15',name='LX',do_erc=True),
            Pin(num='16',name='BootSt',do_erc=True)]),
        Part(name='MAX1811',dest=TEMPLATE,tool=SKIDL,keywords='USB Battery Charger',description='USB Powered Li+ Charger, 4.1V/4.2V battery, 5V input, 0.1/0.5A charging current',ref_prefix='U',num_units=1,fplist=['SOIC*'],do_erc=True,pins=[
            Pin(num='1',name='SELV',do_erc=True),
            Pin(num='2',name='SELI',do_erc=True),
            Pin(num='3',name='GND',func=Pin.PWRIN,do_erc=True),
            Pin(num='4',name='IN',func=Pin.PWRIN,do_erc=True),
            Pin(num='5',name='BATT',func=Pin.PWROUT,do_erc=True),
            Pin(num='6',name='GND',func=Pin.PWRIN,do_erc=True),
            Pin(num='7',name='EN',do_erc=True),
            Pin(num='8',name='~CHG',func=Pin.OPENCOLL,do_erc=True)]),
        Part(name='MCP73812T-420I/OT',dest=TEMPLATE,tool=SKIDL,keywords='Lithium-Ion Battery Charger',description='Simple, Miniature Single-Cell, Fully Integrated Li-Ion / Li-Polymer Charge Management Controllers, 50mA-500mA',ref_prefix='U',num_units=1,fplist=['*SOT-23-5*'],do_erc=True,aliases=['MCP73812T-435I/OT', 'MCP73811T-420I/OT', 'MCP73811T-435I/OT'],pins=[
github xesscorp / skidl / skidl / libs / audio_sklib.py View on Github external
from skidl import SKIDL, TEMPLATE, Part, Pin, SchLib

SKIDL_lib_version = '0.0.1'

audio = SchLib(tool=SKIDL).add_parts(*[
        Part(name='LL1587',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='LM1875',dest=TEMPLATE,tool=SKIDL,keywords='LM1875 Amplifier 20W',description='20W Audio Power Amplifier, TO220-5',ref_prefix='U',num_units=1,fplist=['TO*'],do_erc=True,pins=[
            Pin(num='1',name='IN+',do_erc=True),
            Pin(num='2',name='IN-',do_erc=True),
            Pin(num='3',name='VEE',func=Pin.PWRIN,do_erc=True),
            Pin(num='4',name='OUT',func=Pin.OUTPUT,do_erc=True),
            Pin(num='5',name='VCC',func=Pin.PWRIN,do_erc=True)]),
        Part(name='LM1876',dest=TEMPLATE,tool=SKIDL,keywords='LM1876 Overture Amplifier Dual 20W',description='Dual 20W Overture Seriers Audio Power Amplifier, with Mute Standby Mode, TO220-15 (MultiWatt)',ref_prefix='U',num_units=2,fplist=['TO*'],do_erc=True,pins=[
            Pin(num='2',name='VCC',func=Pin.PWRIN,do_erc=True),
            Pin(num='3',name='OUT',func=Pin.OUTPUT,do_erc=True),
            Pin(num='4',name='VEE',func=Pin.PWRIN,do_erc=True),
            Pin(num='5',name='GND',func=Pin.PWRIN,do_erc=True),
            Pin(num='6',name='MUTE',do_erc=True),
            Pin(num='7',name='IN-',do_erc=True),
            Pin(num='8',name='IN+',do_erc=True),
            Pin(num='9',name='STB',do_erc=True),
            Pin(num='1',name='OUT',func=Pin.OUTPUT,do_erc=True),
            Pin(num='4',name='VEE',func=Pin.PWRIN,do_erc=True),
            Pin(num='10',name='GND',func=Pin.PWRIN,do_erc=True),
github xesscorp / skidl / skidl / libs / supertex_sklib.py View on Github external
Pin(num='3',name='VD',do_erc=True),
            Pin(num='4',name='PWMD',func=Pin.OUTPUT,do_erc=True),
            Pin(num='5',name='CS',do_erc=True),
            Pin(num='6',name='GND',func=Pin.PWRIN,do_erc=True),
            Pin(num='7',name='GATE',func=Pin.OUTPUT,do_erc=True),
            Pin(num='8',name='VDD',func=Pin.PWROUT,do_erc=True)]),
        Part(name='LR8K4-G',dest=TEMPLATE,tool=SKIDL,keywords='High-Voltage Regulator Adjustable Positive',description='30mA 450V High-Voltage Linear Regulator (Adjustable), TO-252 (D-PAK)',ref_prefix='U',num_units=1,fplist=['TO-252*', 'DPAK*'],do_erc=True,pins=[
            Pin(num='1',name='IN',do_erc=True),
            Pin(num='2',name='OUT',func=Pin.PWROUT,do_erc=True),
            Pin(num='3',name='ADJ',do_erc=True)]),
        Part(name='LR8N3-G',dest=TEMPLATE,tool=SKIDL,keywords='High-Voltage Regulator Adjustable Positive',description='30mA 450V High-Voltage Linear Regulator (Adjustable), TO-92',ref_prefix='U',num_units=1,fplist=['TO-92*'],do_erc=True,pins=[
            Pin(num='1',name='IN',do_erc=True),
            Pin(num='2',name='OUT',func=Pin.PWROUT,do_erc=True),
            Pin(num='3',name='ADJ',do_erc=True)]),
        Part(name='LR8N8-G',dest=TEMPLATE,tool=SKIDL,keywords='High-Voltage Regulator Adjustable Positive',description='30mA 450V High-Voltage Linear Regulator (Adjustable), SOT-89',ref_prefix='U',num_units=1,fplist=['SOT*'],do_erc=True,pins=[
            Pin(num='1',name='IN',do_erc=True),
            Pin(num='2',name='OUT',func=Pin.PWROUT,do_erc=True),
            Pin(num='3',name='ADJ',do_erc=True)])])
github xesscorp / skidl / skidl / libs / Worldsemi_sklib.py View on Github external
Pin(num='2',name='DOUT',func=Pin.OUTPUT,do_erc=True),
            Pin(num='3',name='VSS',func=Pin.PWRIN,do_erc=True),
            Pin(num='4',name='DIN',do_erc=True)]),
        Part(name='WS2812S',dest=TEMPLATE,tool=SKIDL,keywords='RGB LED',description='RGB LED with integrated controller',ref_prefix='LED',num_units=1,do_erc=True,aliases=['WS2812'],pins=[
            Pin(num='1',name='DOUT',func=Pin.OUTPUT,do_erc=True),
            Pin(num='2',name='DIN',do_erc=True),
            Pin(num='3',name='VCC',func=Pin.PWRIN,do_erc=True),
            Pin(num='5',name='VDD',func=Pin.PWRIN,do_erc=True),
            Pin(num='6',name='VSS',func=Pin.PWRIN,do_erc=True)]),
        Part(name='WS2822S_A',dest=TEMPLATE,tool=SKIDL,keywords='RGB LED',description='RGB LED with integrated controller',ref_prefix='LED',num_units=1,do_erc=True,pins=[
            Pin(num='1',name='DIN',do_erc=True),
            Pin(num='2',name='ADRIN',do_erc=True),
            Pin(num='3',name='VCC',func=Pin.PWRIN,do_erc=True),
            Pin(num='4',name='VSS',func=Pin.PWRIN,do_erc=True),
            Pin(num='5',name='ADROUT',func=Pin.OUTPUT,do_erc=True),
            Pin(num='6',name='VDD',func=Pin.PWRIN,do_erc=True)]),
        Part(name='WS2822S_B',dest=TEMPLATE,tool=SKIDL,keywords='RGB LED',description='RGB LED with integrated controller',ref_prefix='LED',num_units=1,do_erc=True,pins=[
            Pin(num='1',name='ADROUT',func=Pin.OUTPUT,do_erc=True),
            Pin(num='2',name='VDD',func=Pin.PWRIN,do_erc=True),
            Pin(num='3',name='VSS',func=Pin.PWRIN,do_erc=True),
            Pin(num='4',name='DIN',do_erc=True),
            Pin(num='5',name='ADRIN',do_erc=True),
            Pin(num='6',name='VCC',func=Pin.PWRIN,do_erc=True)])])
github xesscorp / skidl / skidl / libs / regul_sklib.py View on Github external
Pin(num='6',name='TAP',func=Pin.PASSIVE,do_erc=True),
            Pin(num='7',name='FB',func=Pin.PASSIVE,do_erc=True),
            Pin(num='8',name='IN',func=Pin.PWRIN,do_erc=True)]),
        Part(name='SPX2920T-3.3',dest=TEMPLATE,tool=SKIDL,keywords='REGULATOR LDO 5V',description='400mA Low drop-out regulator, Fixed Output 5V, TO-263',ref_prefix='U',num_units=1,fplist=['TO*'],do_erc=True,aliases=['SPX2920T-5.0'],pins=[
            Pin(num='1',name='VI',func=Pin.PWRIN,do_erc=True),
            Pin(num='2',name='GND',func=Pin.PWRIN,do_erc=True),
            Pin(num='3',name='VO',func=Pin.PWROUT,do_erc=True)]),
        Part(name='SPX2920U-3.3',dest=TEMPLATE,tool=SKIDL,keywords='REGULATOR LDO 5V',description='400mA Low drop-out regulator, Fixed Output 5V, TO-220',ref_prefix='U',num_units=1,fplist=['TO*'],do_erc=True,aliases=['SPX2920U-5.0'],pins=[
            Pin(num='1',name='VI',func=Pin.PWRIN,do_erc=True),
            Pin(num='2',name='GND',func=Pin.PWRIN,do_erc=True),
            Pin(num='3',name='VO',func=Pin.PWROUT,do_erc=True)]),
        Part(name='TC1054',dest=TEMPLATE,tool=SKIDL,keywords='LDO regulator voltage',description='150mA Low Dropout Regulator with ERROR output in 5-Pin SOT-23 package',ref_prefix='U',num_units=1,do_erc=True,aliases=['TC1055', 'TC1186'],pins=[
            Pin(num='1',name='Vin',func=Pin.PWRIN,do_erc=True),
            Pin(num='2',name='GND',func=Pin.PWRIN,do_erc=True),
            Pin(num='3',name='~SHDN',do_erc=True),
            Pin(num='4',name='~ERROR',do_erc=True),
            Pin(num='5',name='Vout',func=Pin.PWROUT,do_erc=True)]),
        Part(name='TC1262-33VDB',dest=TEMPLATE,tool=SKIDL,keywords='Voltage Regulator 5.0V 500mA Positive CMOS LDO Microchip',description='500mA Low Dropout CMOS Voltage Regulator, Fixed Output 5.0V, SOT-223',ref_prefix='U',num_units=1,fplist=['SOT-223*'],do_erc=True,aliases=['TC1262-25VDB', 'TC1262-28VDB', 'TC1262-30VDB', 'TC1262-50VDB'],pins=[
            Pin(num='1',name='VIN',func=Pin.PWRIN,do_erc=True),
            Pin(num='2',name='GND',func=Pin.PWRIN,do_erc=True),
            Pin(num='3',name='VOUT',func=Pin.PWROUT,do_erc=True),
            Pin(num='4',name='GND',func=Pin.PWRIN,do_erc=True)]),
        Part(name='TLV70012DCK',dest=TEMPLATE,tool=SKIDL,keywords='200mA LDO Regulator Fixed Positive',description='200 mA Low Dropout Voltage Regulator, Fixed Output 3.3V, SC70-5',ref_prefix='U',num_units=1,fplist=['SC*'],do_erc=True,aliases=['TLV70015DCK', 'TLV70018DCK', 'TLV70025DCK', 'TLV70028DCK', 'TLV70030DCK', 'TLV70033DCK'],pins=[
            Pin(num='1',name='IN',do_erc=True),
            Pin(num='2',name='GND',func=Pin.PWRIN,do_erc=True),
            Pin(num='3',name='EN',do_erc=True),
            Pin(num='5',name='OUT',func=Pin.PWROUT,do_erc=True)]),
        Part(name='TLV70012DDC',dest=TEMPLATE,tool=SKIDL,keywords='200mA LDO Regulator Fixed Positive',description='200 mA Low Dropout Voltage Regulator, Fixed Output 3.6V, SOT-23-5',ref_prefix='U',num_units=1,fplist=['SOT*'],do_erc=True,aliases=['TLV70013DDC', 'TLV70015DDC', 'TLV70018DDC', 'TLV70019DDC', 'TLV70025DDC', 'TLV70030DDC', 'TLV70032DDC', 'TLV70033DDC', 'TLV70036DDC'],pins=[
            Pin(num='1',name='IN',do_erc=True),
            Pin(num='2',name='GND',func=Pin.PWRIN,do_erc=True),
            Pin(num='3',name='EN',do_erc=True),
            Pin(num='5',name='OUT',func=Pin.PWROUT,do_erc=True)]),