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How to use the skidl.Part function in skidl

To help you get started, we’ve selected a few skidl examples, based on popular ways it is used in public projects.

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github xesscorp / skidl / skidl / libs / intel_sklib.py View on Github external
Pin(num='15',name='AD1',func=Pin.BIDIR,do_erc=True),
            Pin(num='25',name='QS0',func=Pin.OUTPUT,do_erc=True),
            Pin(num='35',name='A19/S6',func=Pin.OUTPUT,do_erc=True),
            Pin(num='16',name='AD0',func=Pin.BIDIR,do_erc=True),
            Pin(num='26',name='~S0~',func=Pin.OUTPUT,do_erc=True),
            Pin(num='36',name='A18/S5',func=Pin.OUTPUT,do_erc=True),
            Pin(num='17',name='NMI',do_erc=True),
            Pin(num='27',name='~S1~',func=Pin.OUTPUT,do_erc=True),
            Pin(num='37',name='A17/S4',func=Pin.OUTPUT,do_erc=True),
            Pin(num='18',name='INTR',do_erc=True),
            Pin(num='28',name='~S2~',func=Pin.OUTPUT,do_erc=True),
            Pin(num='38',name='A16/S3',func=Pin.OUTPUT,do_erc=True),
            Pin(num='19',name='CLK',do_erc=True),
            Pin(num='29',name='~LOCK~',func=Pin.OUTPUT,do_erc=True),
            Pin(num='39',name='AD15',func=Pin.BIDIR,do_erc=True)]),
        Part(name='8086_Min_Mode',dest=TEMPLATE,tool=SKIDL,keywords='MPRO',description='8086 (minimum mode), 16-Bit HMOS Microprocessor, PDIP-40',ref_prefix='U',num_units=1,fplist=['DIP*W15.24mm*', 'PDIP*W15.24mm*'],do_erc=True,pins=[
            Pin(num='1',name='GND',func=Pin.PWRIN,do_erc=True),
            Pin(num='2',name='AD14',func=Pin.BIDIR,do_erc=True),
            Pin(num='3',name='AD13',func=Pin.BIDIR,do_erc=True),
            Pin(num='4',name='AD12',func=Pin.BIDIR,do_erc=True),
            Pin(num='5',name='AD11',func=Pin.BIDIR,do_erc=True),
            Pin(num='6',name='AD10',func=Pin.BIDIR,do_erc=True),
            Pin(num='7',name='AD9',func=Pin.BIDIR,do_erc=True),
            Pin(num='8',name='AD8',func=Pin.BIDIR,do_erc=True),
            Pin(num='9',name='AD7',func=Pin.BIDIR,do_erc=True),
            Pin(num='10',name='AD6',func=Pin.BIDIR,do_erc=True),
            Pin(num='20',name='GND',func=Pin.PWRIN,do_erc=True),
            Pin(num='30',name='HLDA',func=Pin.OUTPUT,do_erc=True),
            Pin(num='40',name='VCC',func=Pin.PWRIN,do_erc=True),
            Pin(num='11',name='AD5',func=Pin.BIDIR,do_erc=True),
            Pin(num='21',name='RESET',do_erc=True),
            Pin(num='31',name='HOLD',do_erc=True),
github xesscorp / skidl / skidl / libs / cypress_sklib.py View on Github external
from skidl import SKIDL, TEMPLATE, Part, Pin, SchLib

SKIDL_lib_version = '0.0.1'

cypress = SchLib(tool=SKIDL).add_parts(*[
        Part(name='CY7C185',dest=TEMPLATE,tool=SKIDL,do_erc=True,aliases=['CY7C186']),
        Part(name='CY7C194',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='CY7C199',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='CY7C261',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='CY7C263',dest=TEMPLATE,tool=SKIDL,do_erc=True,aliases=['CY7C264']),
        Part(name='CY7C271',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='CY7C420',dest=TEMPLATE,tool=SKIDL,do_erc=True,aliases=['CY7C421', 'CY7C424', 'CY7C425', 'CY7C428', 'CY7C429']),
        Part(name='CY8C4xx7LQI-4xx',dest=TEMPLATE,tool=SKIDL,keywords='CYPRESS PSOC BLE CY8 CY8C4 ARM CORTEX M0 BLUETOOTH QFN',description='Programmable System-on-Chip With Bluetooth Low Energy, 24/48-MHz ARM® Cortex®-M0 , 56-QFN',ref_prefix='U',num_units=1,fplist=['QFN-56-1EP'],do_erc=True,aliases=['CY8C4127LQI-BL473', 'CY8C4127LQI-BL453', 'CY8C4127LQI-BL483', 'CY8C4127LQI-BL493', 'CY8C4247LQI-BL473', 'CY8C4247LQI-BL453', 'CY8C4247LQI-BL463', 'CY8C4247LQI-BL483', 'CY8C4247LQI-BL493', 'CY8C4247LQQ-BL483'],pins=[
            Pin(num='1',name='VDDD',func=Pin.PWRIN,do_erc=True),
            Pin(num='2',name='XTAL32O/P6.0',func=Pin.BIDIR,do_erc=True),
            Pin(num='3',name='XTAL32I/P6.1',func=Pin.BIDIR,do_erc=True),
            Pin(num='4',name='XRES',do_erc=True),
            Pin(num='5',name='P4.0',func=Pin.BIDIR,do_erc=True),
            Pin(num='6',name='P4.1',func=Pin.BIDIR,do_erc=True),
            Pin(num='7',name='P5.0',func=Pin.BIDIR,do_erc=True),
            Pin(num='8',name='P5.1',func=Pin.BIDIR,do_erc=True),
            Pin(num='9',name='VSSD',func=Pin.PWRIN,do_erc=True),
            Pin(num='10',name='VDDR',func=Pin.PWRIN,do_erc=True),
            Pin(num='20',name='P0.1',func=Pin.BIDIR,do_erc=True),
            Pin(num='30',name='P1.2',func=Pin.BIDIR,do_erc=True),
            Pin(num='40',name='P2.3',func=Pin.BIDIR,do_erc=True),
            Pin(num='50',name='P3.3',func=Pin.BIDIR,do_erc=True),
            Pin(num='11',name='GANT1',func=Pin.PWRIN,do_erc=True),
            Pin(num='21',name='P0.2',func=Pin.BIDIR,do_erc=True),
github xesscorp / skidl / skidl / libs / motor_drivers_sklib.py View on Github external
Pin(num='2',name='1A',do_erc=True),
            Pin(num='3',name='1Y',func=Pin.OUTPUT,do_erc=True),
            Pin(num='4',name='GND',func=Pin.PWRIN,do_erc=True),
            Pin(num='5',name='GND',func=Pin.PWRIN,do_erc=True),
            Pin(num='6',name='2Y',func=Pin.OUTPUT,do_erc=True),
            Pin(num='7',name='2A',do_erc=True),
            Pin(num='8',name='VCC2',func=Pin.PWRIN,do_erc=True),
            Pin(num='9',name='EN3,4',do_erc=True),
            Pin(num='10',name='3A',do_erc=True),
            Pin(num='11',name='3A',func=Pin.OUTPUT,do_erc=True),
            Pin(num='12',name='GND',func=Pin.PWRIN,do_erc=True),
            Pin(num='13',name='GND',func=Pin.PWRIN,do_erc=True),
            Pin(num='14',name='4Y',func=Pin.OUTPUT,do_erc=True),
            Pin(num='15',name='4A',do_erc=True),
            Pin(num='16',name='VCC1',func=Pin.PWRIN,do_erc=True)]),
        Part(name='L298(H)N',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='L298P',dest=TEMPLATE,tool=SKIDL,keywords='H-bridge motor driver',description='Dual full bridge motor driver, up to 46V, 4A',ref_prefix='U',num_units=1,do_erc=True,pins=[
            Pin(num='1',name='GND',func=Pin.PWRIN,do_erc=True),
            Pin(num='2',name='SENSE_A',func=Pin.PWRIN,do_erc=True),
            Pin(num='3',name='NC',func=Pin.NOCONNECT,do_erc=True),
            Pin(num='4',name='OUT1',func=Pin.OUTPUT,do_erc=True),
            Pin(num='5',name='OUT2',func=Pin.OUTPUT,do_erc=True),
            Pin(num='6',name='Vs',func=Pin.PWRIN,do_erc=True),
            Pin(num='7',name='IN1',do_erc=True),
            Pin(num='8',name='EnA',do_erc=True),
            Pin(num='9',name='IN2',do_erc=True),
            Pin(num='10',name='GND',func=Pin.PWRIN,do_erc=True),
            Pin(num='20',name='GND',func=Pin.PWRIN,do_erc=True),
            Pin(num='11',name='GND',func=Pin.PWRIN,do_erc=True),
            Pin(num='12',name='Vss',func=Pin.PWRIN,do_erc=True),
            Pin(num='13',name='IN3',do_erc=True),
            Pin(num='14',name='EnB',do_erc=True),
github xesscorp / skidl / skidl / libs / pspice_sklib.py View on Github external
from skidl import SKIDL, TEMPLATE, Part, Pin, SchLib

SKIDL_lib_version = '0.0.1'

pspice = SchLib(tool=SKIDL).add_parts(*[
        Part(name='0',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='CAP',dest=TEMPLATE,tool=SKIDL,do_erc=True,aliases=['C']),
        Part(name='DIODE',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='INDUCTOR',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='ISOURCE',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='QNPN',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='QPNP',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='R',dest=TEMPLATE,tool=SKIDL,keywords='R DEV',description='Resistance',ref_prefix='R',num_units=1,do_erc=True,pins=[
            Pin(num='1',name='~',func=Pin.PASSIVE,do_erc=True),
            Pin(num='2',name='~',func=Pin.PASSIVE,do_erc=True)]),
        Part(name='VSOURCE',dest=TEMPLATE,tool=SKIDL,do_erc=True)])
github xesscorp / skidl / skidl / libs / cmos_ieee_sklib.py View on Github external
Part(name='4010',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='40104',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='40106',dest=TEMPLATE,tool=SKIDL,do_erc=True,aliases=['4584']),
        Part(name='4011',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='40110',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='4012',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='4013',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='4014',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='4015',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='4016',dest=TEMPLATE,tool=SKIDL,do_erc=True,aliases=['4066']),
        Part(name='4017',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='40174',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='40175',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='4018',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='4019',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='40192',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='40193',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='40194',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='4020',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='4021',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='4022',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='4023',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='4024',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='40240',dest=TEMPLATE,tool=SKIDL,do_erc=True,aliases=['40244']),
        Part(name='40245',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='4025',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='4027',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='4028',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='4029',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='4030',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='40373',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='40374',dest=TEMPLATE,tool=SKIDL,do_erc=True),
github xesscorp / skidl / skidl / libs / allegro_sklib.py View on Github external
from skidl import SKIDL, TEMPLATE, Part, Pin, SchLib

SKIDL_lib_version = '0.0.1'

allegro = SchLib(tool=SKIDL).add_parts(*[
        Part(name='ACS706ELC-05C',dest=TEMPLATE,tool=SKIDL,keywords='hall effect current monitor sensor isolated obsolete',description='15A, Hall Effect Linear Current Sensor, SO-8, OBSOLETE',ref_prefix='U',num_units=1,fplist=['SOIC*3.9x4.9mm*Pitch1.27mm*'],do_erc=True,pins=[
            Pin(num='1',name='IP+',func=Pin.PASSIVE,do_erc=True),
            Pin(num='2',name='IP+',func=Pin.PASSIVE,do_erc=True),
            Pin(num='3',name='IP-',func=Pin.PASSIVE,do_erc=True),
            Pin(num='4',name='IP-',func=Pin.PASSIVE,do_erc=True),
            Pin(num='5',name='GND',func=Pin.PWRIN,do_erc=True),
            Pin(num='6',name='NC',func=Pin.NOCONNECT,do_erc=True),
            Pin(num='7',name='VIout',func=Pin.OUTPUT,do_erc=True),
            Pin(num='8',name='VCC',func=Pin.PWRIN,do_erc=True)]),
        Part(name='ACS711xLCTR-12AB',dest=TEMPLATE,tool=SKIDL,keywords='hall effect current monitor sensor isolated',description='±25A, Bidirectional, hall-effect current sensor, +3.3V supply, 55mV/A, SO-8',ref_prefix='U',num_units=1,fplist=['SOIC*3.9x4.9mm*Pitch1.27mm*'],do_erc=True,aliases=['ACS711xLCTR-25AB'],pins=[
            Pin(num='1',name='IP+',func=Pin.PASSIVE,do_erc=True),
            Pin(num='2',name='IP+',func=Pin.PASSIVE,do_erc=True),
            Pin(num='3',name='IP-',func=Pin.PASSIVE,do_erc=True),
            Pin(num='4',name='IP-',func=Pin.PASSIVE,do_erc=True),
            Pin(num='5',name='GND',func=Pin.PWRIN,do_erc=True),
            Pin(num='6',name='~FAULT',func=Pin.OUTPUT,do_erc=True),
            Pin(num='7',name='VIout',func=Pin.OUTPUT,do_erc=True),
github xesscorp / skidl / skidl / libs / ESD_Protection_sklib.py View on Github external
Pin(num='5',name='K',do_erc=True)]),
        Part(name='SP0505BAHT',dest=TEMPLATE,tool=SKIDL,keywords='usb esd protection suppression transient',description='TVS Diode Array, 5.5V Standoff, 5 Channels, SOT-23-6 package',ref_prefix='D',num_units=1,fplist=['SOT-23*'],do_erc=True,pins=[
            Pin(num='2',name='A',do_erc=True),
            Pin(num='1',name='K',do_erc=True),
            Pin(num='3',name='K',do_erc=True),
            Pin(num='4',name='K',do_erc=True),
            Pin(num='5',name='K',do_erc=True),
            Pin(num='6',name='K',do_erc=True)]),
        Part(name='SP0505BAJT',dest=TEMPLATE,tool=SKIDL,keywords='usb esd protection suppression transient',description='TVS Diode Array, 5.5V Standoff, 5 Channels, SC-70-6 package',ref_prefix='D',num_units=1,fplist=['SC-70*'],do_erc=True,pins=[
            Pin(num='2',name='A',do_erc=True),
            Pin(num='1',name='K',do_erc=True),
            Pin(num='3',name='K',do_erc=True),
            Pin(num='4',name='K',do_erc=True),
            Pin(num='5',name='K',do_erc=True),
            Pin(num='6',name='K',do_erc=True)]),
        Part(name='SRV05',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='TPD2EUSB30',dest=TEMPLATE,tool=SKIDL,keywords='ESD protection USB 3.0',description='2 channel ESD protection for super-speed USB 3.0',ref_prefix='U',num_units=1,fplist=['DRT*'],do_erc=True,pins=[
            Pin(num='1',name='D+',func=Pin.PASSIVE,do_erc=True),
            Pin(num='2',name='D-',func=Pin.PASSIVE,do_erc=True),
            Pin(num='3',name='GND',func=Pin.PWRIN,do_erc=True)]),
        Part(name='TPD2S017',dest=TEMPLATE,tool=SKIDL,do_erc=True),
        Part(name='TPD4EUSB30',dest=TEMPLATE,tool=SKIDL,keywords='ESD protection USB 3.0',description='4 channel ESD protection for super-speed USB 3.0',ref_prefix='U',num_units=1,fplist=['USON*2.5x1.0mm*Pitch0.5mm*'],do_erc=True,pins=[
            Pin(num='1',name='D1+',do_erc=True),
            Pin(num='2',name='D1-',do_erc=True),
            Pin(num='3',name='GND',do_erc=True),
            Pin(num='4',name='D2+',do_erc=True),
            Pin(num='5',name='D2-',do_erc=True),
            Pin(num='6',name='NC',func=Pin.NOCONNECT,do_erc=True),
            Pin(num='7',name='NC',func=Pin.NOCONNECT,do_erc=True),
            Pin(num='8',name='GND',do_erc=True),
            Pin(num='9',name='NC',func=Pin.NOCONNECT,do_erc=True),
            Pin(num='10',name='NC',func=Pin.NOCONNECT,do_erc=True)]),
github xesscorp / skidl / skidl / libs / leds_sklib.py View on Github external
from skidl import SKIDL, TEMPLATE, Part, Pin, SchLib

SKIDL_lib_version = '0.0.1'

leds = SchLib(tool=SKIDL).add_parts(*[
        Part(name='LED_Cree_XHP50_12V',dest=TEMPLATE,tool=SKIDL,keywords='led diode',description='XLamp® XHP50 LED, 12V footprint (all 4 LEDs in series)',ref_prefix='D',num_units=1,fplist=['LED?CREE?XHP50?12V*'],do_erc=True,pins=[
            Pin(num='1',name='K',func=Pin.PASSIVE,do_erc=True),
            Pin(num='2',name='A',func=Pin.PASSIVE,do_erc=True),
            Pin(num='3',name='PAD',func=Pin.PASSIVE,do_erc=True)]),
        Part(name='LED_Cree_XHP50_6V',dest=TEMPLATE,tool=SKIDL,keywords='led diode',description='XLamp® XHP50 LED, 6V footprint (2x2 serial LEDs in parallel)',ref_prefix='D',num_units=1,fplist=['LED?CREE?XHP50?6V*'],do_erc=True,pins=[
            Pin(num='1',name='K',func=Pin.PASSIVE,do_erc=True),
            Pin(num='2',name='A',func=Pin.PASSIVE,do_erc=True),
            Pin(num='3',name='PAD',func=Pin.PASSIVE,do_erc=True)]),
        Part(name='LED_Cree_XHP70_12V',dest=TEMPLATE,tool=SKIDL,keywords='led diode',description='XLamp® XHP70 LED, 12V footprint (all 4 LEDs in series)',ref_prefix='D',num_units=1,fplist=['LED?CREE?XHP70?12V*'],do_erc=True,pins=[
            Pin(num='1',name='K',func=Pin.PASSIVE,do_erc=True),
            Pin(num='2',name='A',func=Pin.PASSIVE,do_erc=True),
            Pin(num='3',name='PAD',func=Pin.PASSIVE,do_erc=True)]),
        Part(name='LED_Cree_XHP70_6V',dest=TEMPLATE,tool=SKIDL,keywords='led diode',description='XLamp® XHP70 LED, 6V footprint (2x2 serial LEDs in parallel)',ref_prefix='D',num_units=1,fplist=['LED?CREE?XHP70?6V*'],do_erc=True,pins=[
            Pin(num='1',name='K',func=Pin.PASSIVE,do_erc=True),
            Pin(num='2',name='A',func=Pin.PASSIVE,do_erc=True),
            Pin(num='3',name='PAD',func=Pin.PASSIVE,do_erc=True)])])
github xesscorp / skidl / skidl / libs / display_sklib.py View on Github external
Part(name='DISPLAY',dest=TEMPLATE,tool=SKIDL,keywords='DEV',description='Afficheur LCD nLignes',ref_prefix='S',num_units=1,do_erc=True,pins=[
            Pin(num='1',name='GND',func=Pin.PWRIN,do_erc=True),
            Pin(num='2',name='VCC',func=Pin.PWRIN,do_erc=True),
            Pin(num='3',name='VLCD',do_erc=True),
            Pin(num='4',name='RS',do_erc=True),
            Pin(num='5',name='R/W',do_erc=True),
            Pin(num='6',name='CS',do_erc=True),
            Pin(num='7',name='D0',func=Pin.TRISTATE,do_erc=True),
            Pin(num='8',name='D1',func=Pin.TRISTATE,do_erc=True),
            Pin(num='9',name='D2',func=Pin.TRISTATE,do_erc=True),
            Pin(num='10',name='D3',func=Pin.TRISTATE,do_erc=True),
            Pin(num='11',name='D4',func=Pin.TRISTATE,do_erc=True),
            Pin(num='12',name='D5',func=Pin.TRISTATE,do_erc=True),
            Pin(num='13',name='D6',func=Pin.TRISTATE,do_erc=True),
            Pin(num='14',name='D7',func=Pin.TRISTATE,do_erc=True)]),
        Part(name='DISPLAY_3_LIGNE',dest=TEMPLATE,tool=SKIDL,description='DISPLAY EA7123-12C',ref_prefix='S',num_units=1,do_erc=True,pins=[
            Pin(num='1',name='GND',func=Pin.PWRIN,do_erc=True),
            Pin(num='2',name='VCC',func=Pin.PWRIN,do_erc=True),
            Pin(num='3',name='VLCD',do_erc=True),
            Pin(num='4',name='VO',do_erc=True),
            Pin(num='5',name='SDA',do_erc=True),
            Pin(num='6',name='SCL',do_erc=True)]),
        Part(name='DOT-BAR',dest=TEMPLATE,tool=SKIDL,keywords='BAR DOT',description='GRAPH unit',ref_prefix='BAR',num_units=10,do_erc=True,pins=[
            Pin(num='1',name='A',func=Pin.PASSIVE,do_erc=True),
            Pin(num='20',name='K',func=Pin.PASSIVE,do_erc=True),
            Pin(num='2',name='A',func=Pin.PASSIVE,do_erc=True),
            Pin(num='19',name='K',func=Pin.PASSIVE,do_erc=True),
            Pin(num='3',name='A',func=Pin.PASSIVE,do_erc=True),
            Pin(num='18',name='K',func=Pin.PASSIVE,do_erc=True),
            Pin(num='4',name='A',func=Pin.PASSIVE,do_erc=True),
            Pin(num='17',name='K',func=Pin.PASSIVE,do_erc=True),
            Pin(num='5',name='A',func=Pin.PASSIVE,do_erc=True),
github xesscorp / skidl / skidl / libs / 74xgxx_sklib.py View on Github external
Pin(num='1',name='~',do_erc=True),
            Pin(num='7',name='~',func=Pin.OUTPUT,do_erc=True),
            Pin(num='2',name='~',func=Pin.OUTPUT,do_erc=True),
            Pin(num='6',name='~',do_erc=True),
            Pin(num='3',name='~',do_erc=True),
            Pin(num='5',name='~',func=Pin.OUTPUT,do_erc=True)]),
        Part(name='74LVC3G06',dest=TEMPLATE,tool=SKIDL,keywords='Triple Gate NOT Open Drain LVC CMOS',description='Triple NOT Gate w/ Open Drain, Low-Voltage CMOS',ref_prefix='U',num_units=3,fplist=['SSOP*', 'VSSOP*'],do_erc=True,pins=[
            Pin(num='4',name='GND',func=Pin.PWRIN,do_erc=True),
            Pin(num='8',name='VCC',func=Pin.PWRIN,do_erc=True),
            Pin(num='1',name='~',do_erc=True),
            Pin(num='7',name='~',func=Pin.OPENCOLL,do_erc=True),
            Pin(num='2',name='~',func=Pin.OPENCOLL,do_erc=True),
            Pin(num='6',name='~',do_erc=True),
            Pin(num='3',name='~',do_erc=True),
            Pin(num='5',name='~',func=Pin.OPENCOLL,do_erc=True)]),
        Part(name='74LVC3G07',dest=TEMPLATE,tool=SKIDL,keywords='Triple Buff Open Drain LVC CMOS',description='Triple Buffer w/ Open Drain, Low-Voltage CMOS',ref_prefix='U',num_units=3,fplist=['SSOP*', 'VSSOP*'],do_erc=True,pins=[
            Pin(num='4',name='GND',func=Pin.PWRIN,do_erc=True),
            Pin(num='8',name='VCC',func=Pin.PWRIN,do_erc=True),
            Pin(num='1',name='~',do_erc=True),
            Pin(num='7',name='~',func=Pin.OPENCOLL,do_erc=True),
            Pin(num='2',name='~',func=Pin.OPENCOLL,do_erc=True),
            Pin(num='6',name='~',do_erc=True),
            Pin(num='3',name='~',do_erc=True),
            Pin(num='5',name='~',func=Pin.OPENCOLL,do_erc=True)]),
        Part(name='74LVC3G14',dest=TEMPLATE,tool=SKIDL,keywords='Triple NOT Schmidt LVC CMOS',description='Triple NOT Gate Schmidt, Low-Voltage CMOS',ref_prefix='U',num_units=3,fplist=['SSOP*', 'VSSOP*'],do_erc=True,pins=[
            Pin(num='4',name='GND',func=Pin.PWRIN,do_erc=True),
            Pin(num='8',name='VCC',func=Pin.PWRIN,do_erc=True),
            Pin(num='1',name='~',do_erc=True),
            Pin(num='7',name='~',func=Pin.OUTPUT,do_erc=True),
            Pin(num='2',name='~',func=Pin.OUTPUT,do_erc=True),
            Pin(num='6',name='~',do_erc=True),
            Pin(num='3',name='~',do_erc=True),

skidl

A Python package for textually describing electronic circuit schematics.

GitHub
MIT
Latest version published 9 months ago

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67 / 100
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