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How to use the pyocd.coresight.cortex_m.CortexM.RegisterInfo function in pyocd

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github XIVN1987 / DAPCmdr / pyocd / coresight / cortex_m.py View on Github external
regs_system_armv7_only = [
        #            Name       bitsize     type            group
        RegisterInfo('basepri',     32,     'int',          'system'),
        RegisterInfo('faultmask',   32,     'int',          'system'),
        ]

    regs_float = [
        #            Name       bitsize     type            group
        RegisterInfo('fpscr',   32,         'int',          'float'),
        RegisterInfo('d0' ,     64,         'ieee_double',  'float'),
        RegisterInfo('d1' ,     64,         'ieee_double',  'float'),
        RegisterInfo('d2' ,     64,         'ieee_double',  'float'),
        RegisterInfo('d3' ,     64,         'ieee_double',  'float'),
        RegisterInfo('d4' ,     64,         'ieee_double',  'float'),
        RegisterInfo('d5' ,     64,         'ieee_double',  'float'),
        RegisterInfo('d6' ,     64,         'ieee_double',  'float'),
        RegisterInfo('d7' ,     64,         'ieee_double',  'float'),
        RegisterInfo('d8' ,     64,         'ieee_double',  'float'),
        RegisterInfo('d9' ,     64,         'ieee_double',  'float'),
        RegisterInfo('d10',     64,         'ieee_double',  'float'),
        RegisterInfo('d11',     64,         'ieee_double',  'float'),
        RegisterInfo('d12',     64,         'ieee_double',  'float'),
        RegisterInfo('d13',     64,         'ieee_double',  'float'),
        RegisterInfo('d14',     64,         'ieee_double',  'float'),
        RegisterInfo('d15',     64,         'ieee_double',  'float'),
        ]

    @classmethod
    def factory(cls, ap, cmpid, address):
        # Create a new core instance.
        root = ap.dp.target
        core = cls(root, ap, root.memory_map, root._new_core_num, cmpid, address)
github XIVN1987 / DAPCmdr / pyocd / coresight / cortex_m.py View on Github external
self.gdb_xml_attrib['bitsize'] = str(bitsize)
            self.gdb_xml_attrib['type'] = str(reg_type)
            self.gdb_xml_attrib['group'] = str(reg_group)

    regs_general = [
        #            Name       bitsize     type            group
        RegisterInfo('r0',      32,         'int',          'general'),
        RegisterInfo('r1',      32,         'int',          'general'),
        RegisterInfo('r2',      32,         'int',          'general'),
        RegisterInfo('r3',      32,         'int',          'general'),
        RegisterInfo('r4',      32,         'int',          'general'),
        RegisterInfo('r5',      32,         'int',          'general'),
        RegisterInfo('r6',      32,         'int',          'general'),
        RegisterInfo('r7',      32,         'int',          'general'),
        RegisterInfo('r8',      32,         'int',          'general'),
        RegisterInfo('r9',      32,         'int',          'general'),
        RegisterInfo('r10',     32,         'int',          'general'),
        RegisterInfo('r11',     32,         'int',          'general'),
        RegisterInfo('r12',     32,         'int',          'general'),
        RegisterInfo('sp',      32,         'data_ptr',     'general'),
        RegisterInfo('lr',      32,         'int',          'general'),
        RegisterInfo('pc',      32,         'code_ptr',     'general'),
        RegisterInfo('xpsr',    32,         'int',          'general'),
        RegisterInfo('msp',     32,         'data_ptr',     'system'),
        RegisterInfo('psp',     32,         'data_ptr',     'system'),
        RegisterInfo('primask', 32,         'int',          'system'),
        RegisterInfo('control', 32,         'int',          'system'),
        ]

    regs_system_armv7_only = [
        #            Name       bitsize     type            group
        RegisterInfo('basepri',     32,     'int',          'system'),
github XIVN1987 / DAPCmdr / pyocd / coresight / cortex_m.py View on Github external
regs_general = [
        #            Name       bitsize     type            group
        RegisterInfo('r0',      32,         'int',          'general'),
        RegisterInfo('r1',      32,         'int',          'general'),
        RegisterInfo('r2',      32,         'int',          'general'),
        RegisterInfo('r3',      32,         'int',          'general'),
        RegisterInfo('r4',      32,         'int',          'general'),
        RegisterInfo('r5',      32,         'int',          'general'),
        RegisterInfo('r6',      32,         'int',          'general'),
        RegisterInfo('r7',      32,         'int',          'general'),
        RegisterInfo('r8',      32,         'int',          'general'),
        RegisterInfo('r9',      32,         'int',          'general'),
        RegisterInfo('r10',     32,         'int',          'general'),
        RegisterInfo('r11',     32,         'int',          'general'),
        RegisterInfo('r12',     32,         'int',          'general'),
        RegisterInfo('sp',      32,         'data_ptr',     'general'),
        RegisterInfo('lr',      32,         'int',          'general'),
        RegisterInfo('pc',      32,         'code_ptr',     'general'),
        RegisterInfo('xpsr',    32,         'int',          'general'),
        RegisterInfo('msp',     32,         'data_ptr',     'system'),
        RegisterInfo('psp',     32,         'data_ptr',     'system'),
        RegisterInfo('primask', 32,         'int',          'system'),
        RegisterInfo('control', 32,         'int',          'system'),
        ]

    regs_system_armv7_only = [
        #            Name       bitsize     type            group
        RegisterInfo('basepri',     32,     'int',          'system'),
        RegisterInfo('faultmask',   32,     'int',          'system'),
        ]
github XIVN1987 / DAPCmdr / pyocd / coresight / cortex_m.py View on Github external
RegisterInfo('faultmask',   32,     'int',          'system'),
        ]

    regs_float = [
        #            Name       bitsize     type            group
        RegisterInfo('fpscr',   32,         'int',          'float'),
        RegisterInfo('d0' ,     64,         'ieee_double',  'float'),
        RegisterInfo('d1' ,     64,         'ieee_double',  'float'),
        RegisterInfo('d2' ,     64,         'ieee_double',  'float'),
        RegisterInfo('d3' ,     64,         'ieee_double',  'float'),
        RegisterInfo('d4' ,     64,         'ieee_double',  'float'),
        RegisterInfo('d5' ,     64,         'ieee_double',  'float'),
        RegisterInfo('d6' ,     64,         'ieee_double',  'float'),
        RegisterInfo('d7' ,     64,         'ieee_double',  'float'),
        RegisterInfo('d8' ,     64,         'ieee_double',  'float'),
        RegisterInfo('d9' ,     64,         'ieee_double',  'float'),
        RegisterInfo('d10',     64,         'ieee_double',  'float'),
        RegisterInfo('d11',     64,         'ieee_double',  'float'),
        RegisterInfo('d12',     64,         'ieee_double',  'float'),
        RegisterInfo('d13',     64,         'ieee_double',  'float'),
        RegisterInfo('d14',     64,         'ieee_double',  'float'),
        RegisterInfo('d15',     64,         'ieee_double',  'float'),
        ]

    @classmethod
    def factory(cls, ap, cmpid, address):
        # Create a new core instance.
        root = ap.dp.target
        core = cls(root, ap, root.memory_map, root._new_core_num, cmpid, address)
        
        # Associate this core with the AP.
        if ap.core is not None:
github XIVN1987 / DAPCmdr / pyocd / coresight / cortex_m.py View on Github external
def __init__(self, name, bitsize, reg_type, reg_group):
            self.name = name
            self.reg_num = CORE_REGISTER[name]
            self.bitsize = bitsize
            self.gdb_xml_attrib = {}
            self.gdb_xml_attrib['name'] = str(name)
            self.gdb_xml_attrib['bitsize'] = str(bitsize)
            self.gdb_xml_attrib['type'] = str(reg_type)
            self.gdb_xml_attrib['group'] = str(reg_group)

    regs_general = [
        #            Name       bitsize     type            group
        RegisterInfo('r0',      32,         'int',          'general'),
        RegisterInfo('r1',      32,         'int',          'general'),
        RegisterInfo('r2',      32,         'int',          'general'),
        RegisterInfo('r3',      32,         'int',          'general'),
        RegisterInfo('r4',      32,         'int',          'general'),
        RegisterInfo('r5',      32,         'int',          'general'),
        RegisterInfo('r6',      32,         'int',          'general'),
        RegisterInfo('r7',      32,         'int',          'general'),
        RegisterInfo('r8',      32,         'int',          'general'),
        RegisterInfo('r9',      32,         'int',          'general'),
        RegisterInfo('r10',     32,         'int',          'general'),
        RegisterInfo('r11',     32,         'int',          'general'),
        RegisterInfo('r12',     32,         'int',          'general'),
        RegisterInfo('sp',      32,         'data_ptr',     'general'),
        RegisterInfo('lr',      32,         'int',          'general'),
        RegisterInfo('pc',      32,         'code_ptr',     'general'),
        RegisterInfo('xpsr',    32,         'int',          'general'),
        RegisterInfo('msp',     32,         'data_ptr',     'system'),
        RegisterInfo('psp',     32,         'data_ptr',     'system'),
        RegisterInfo('primask', 32,         'int',          'system'),
github XIVN1987 / DAPCmdr / pyocd / coresight / cortex_m.py View on Github external
MVFR2_VFP_MISC_SHIFT = 4

    class RegisterInfo(object):
        def __init__(self, name, bitsize, reg_type, reg_group):
            self.name = name
            self.reg_num = CORE_REGISTER[name]
            self.bitsize = bitsize
            self.gdb_xml_attrib = {}
            self.gdb_xml_attrib['name'] = str(name)
            self.gdb_xml_attrib['bitsize'] = str(bitsize)
            self.gdb_xml_attrib['type'] = str(reg_type)
            self.gdb_xml_attrib['group'] = str(reg_group)

    regs_general = [
        #            Name       bitsize     type            group
        RegisterInfo('r0',      32,         'int',          'general'),
        RegisterInfo('r1',      32,         'int',          'general'),
        RegisterInfo('r2',      32,         'int',          'general'),
        RegisterInfo('r3',      32,         'int',          'general'),
        RegisterInfo('r4',      32,         'int',          'general'),
        RegisterInfo('r5',      32,         'int',          'general'),
        RegisterInfo('r6',      32,         'int',          'general'),
        RegisterInfo('r7',      32,         'int',          'general'),
        RegisterInfo('r8',      32,         'int',          'general'),
        RegisterInfo('r9',      32,         'int',          'general'),
        RegisterInfo('r10',     32,         'int',          'general'),
        RegisterInfo('r11',     32,         'int',          'general'),
        RegisterInfo('r12',     32,         'int',          'general'),
        RegisterInfo('sp',      32,         'data_ptr',     'general'),
        RegisterInfo('lr',      32,         'int',          'general'),
        RegisterInfo('pc',      32,         'code_ptr',     'general'),
        RegisterInfo('xpsr',    32,         'int',          'general'),

pyocd

Cortex-M debugger for Python

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Apache-2.0
Latest version published 1 year ago

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69 / 100
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