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else:
mask = CortexM.NVIC_AIRCR_SYSRESETREQ
try:
self.write_memory(CortexM.NVIC_AIRCR, CortexM.NVIC_AIRCR_VECTKEY | mask)
self.flush()
except exceptions.TransferError:
self.flush()
with Timeout(5.0) as t_o:
while t_o.check():
try:
dhcsr_reg = self.read32(CortexM.DHCSR)
if (dhcsr_reg & CortexM.S_RESET_ST) == 0:
break
except exceptions.TransferError:
self.flush()
self._ap.dp.init()
self._ap.dp.power_up_debug()
sleep(0.01)
self.session.notify(Target.EVENT_POST_RESET, self)
# Handle transfer faults specially so we can assign the address info.
if status != Status.JTAG_OK:
error_message = Status.get_error_message(status)
if status in self._MEM_FAULT_ERRORS:
# Clear sticky errors.
self._clear_sticky_error()
exc = exceptions.TransferFaultError()
exc.fault_address = faultAddr
exc.fault_length = thisTransferSize - (faultAddr - addr)
raise exc
elif status in self._ERROR_CLASSES:
raise self._ERROR_CLASSES[status](error_message)
elif status != Status.JTAG_OK:
raise exceptions.ProbeError(error_message)
return result
if writeData is not None:
if LOG_USB_DATA:
log.debug(" USB OUT> %s" % ' '.join(['%02x' % i for i in writeData]))
count = self._ep_out.write(writeData, timeout)
assert count == len(writeData)
# Optional data in phase.
if readSize is not None:
if LOG_USB_DATA:
log.debug(" USB IN < (%d bytes)" % readSize)
data = self._read(readSize)
if LOG_USB_DATA:
log.debug(" USB IN < %s" % ' '.join(['%02x' % i for i in data]))
return data
except usb.core.USBError as exc:
six.raise_from(exceptions.ProbeError("USB Error: %s" % exc), exc)
return None
return str(bytearray(data))
target_str = ''
# TODO - use memory map to make sure we don't try to read off the end of memory
# Limit string size in case it isn't terminated.
while len(target_str) < MAX_STRING_LENGTH:
try:
# Read 32 bytes at a time for efficiency.
data = self.context.read_memory_block8(ptr, 32)
terminator = data.index(0)
# Found a null terminator, append data up to but not including the null
# and then exit the loop.
target_str += str(bytearray(data[:terminator]))
break
except exceptions.TransferError:
# Failed to read some or all of the string.
break
except ValueError:
# No null terminator was found. Append all of data.
target_str += str(bytearray(data))
ptr += 32
return target_str
def wait_halted(self):
with Timeout(5.0) as t_o:
while t_o.check():
try:
if not self.is_running():
break
except exceptions.TransferError:
self.flush()
sleep(0.01)
else:
raise exceptions.TimeoutError("Timeout waiting for target halt")
def __iter__(self):
node = self._context.read32(self._list)
while (node != 0):
try:
yield node
# Read next list node pointer.
node = self._context.read32(node + self._list_node_next_offset)
except exceptions.TransferError:
LOG.warning("TransferError while reading list elements (list=0x%08x, node=0x%08x), terminating list", self._list, node)
node = 0
self.ap.dp.link.reset() # self.session.probe.reset()
elif reset_type is Target.ResetType.SW_EMULATED:
self._perform_emulated_reset()
else:
if reset_type is Target.ResetType.SW_SYSRESETREQ:
mask = CortexM.NVIC_AIRCR_SYSRESETREQ
elif reset_type is Target.ResetType.SW_VECTRESET:
mask = CortexM.NVIC_AIRCR_VECTRESET
else:
raise RuntimeError("internal error, unhandled reset type")
try:
self.write_memory(CortexM.NVIC_AIRCR, CortexM.NVIC_AIRCR_VECTKEY | mask)
# Without a flush a transfer error can occur
self.flush()
except exceptions.TransferError:
self.flush()
# Wait until the target is halted
with Timeout(HALT_TIMEOUT) as to:
while to.check():
if self.mdm_ap.read_reg(MDM_CORE_STATUS) & MDM_CORE_STATUS_CM4_HALTED != MDM_CORE_STATUS_CM4_HALTED:
break
LOG.debug("Waiting for mdm halt")
sleep(0.01)
else:
raise exceptions.TimeoutError("Timed out waiting for core to halt")
# release MDM halt once it has taken effect in the DHCSR
self.mdm_ap.write_reg(MDM_CTRL, 0)
# sanity check that the target is still halted
if self.get_state() == Target.State.RUNNING:
raise exceptions.DebugError("Target failed to stay halted during init sequence")
## Port number to use to indicate DP registers.
DP_PORT = 0xffff
## Map to convert from STLink error response codes to exception classes.
_ERROR_CLASSES = {
# AP protocol errors
Status.SWD_AP_WAIT: exceptions.TransferTimeoutError,
Status.SWD_AP_FAULT: exceptions.TransferFaultError,
Status.SWD_AP_ERROR: exceptions.TransferError,
Status.SWD_AP_PARITY_ERROR: exceptions.TransferError,
# DP protocol errors
Status.SWD_DP_WAIT: exceptions.TransferTimeoutError,
Status.SWD_DP_FAULT: exceptions.TransferFaultError,
Status.SWD_DP_ERROR: exceptions.TransferError,
Status.SWD_DP_PARITY_ERROR: exceptions.TransferError,
# High level transaction errors
Status.SWD_AP_WDATA_ERROR: exceptions.TransferFaultError,
Status.SWD_AP_STICKY_ERROR: exceptions.TransferError,
Status.SWD_AP_STICKYORUN_ERROR: exceptions.TransferError,
}
## These errors indicate a memory fault.
_MEM_FAULT_ERRORS = (
Status.JTAG_UNKNOWN_ERROR, # Returned in some cases by older STLink firmware.
Status.SWD_AP_FAULT,
Status.SWD_DP_FAULT,
Status.SWD_AP_WDATA_ERROR,
Status.SWD_AP_STICKY_ERROR,
)
# Give the delegate a chance to overide reset. If the delegate returns True, then it
# handled the reset on its own.
if not self.call_delegate('will_reset', core=self, reset_type=reset_type):
self._perform_reset(reset_type)
self.call_delegate('did_reset', core=self, reset_type=reset_type)
# Now wait for the system to come out of reset. Keep reading the DHCSR until
# we get a good response with S_RESET_ST cleared, or we time out.
with timeout.Timeout(2.0) as t_o:
while t_o.check():
try:
dhcsr = self.read32(CortexM.DHCSR)
if (dhcsr & CortexM.S_RESET_ST) == 0:
break
except exceptions.TransferError:
self.flush()
sleep(0.01)
self.notify(Notification(event=Target.EVENT_POST_RESET, source=self))