How to use the pyocd.core.memory_map.RamRegion function in pyocd

def test_x(self):
        ramrgn = RamRegion(name='core0 ram', start=0x1fffa000, length=0x18000)
        assert ramrgn.contains_range(0x1fffc9f8, end=0x1fffc9fc)
        assert ramrgn.intersects_range(0x1fffc9f8, end=0x1fffc9fc)
        dualMap = MemoryMap(
            FlashRegion(name='flash', start=0, length=0x80000, blocksize=0x800, is_boot_memory=True),
            RomRegion(name='core1 imem alias', start=0x1d200000, length=0x40000),
            ramrgn,
            RomRegion(name='core1 imem', start=0x2d200000, length=0x40000),
            RamRegion(name='core1 dmem', start=0x2d300000, length=0x8000),
            RamRegion(name='usb ram', start=0x40100000, length=0x800)
            )
        rgns = dualMap.get_intersecting_regions(0x1fffc9f8, end=0x1fffc9fc)
        assert len(rgns) > 0

memoryMap = MemoryMap(
        FlashRegion( start=0x08000000, length=0x10000,  sector_size=0x4000,
                                                        page_size=0x1000, 
                                                        is_boot_memory=True,
                                                        erase_all_weight=CHIP_ERASE_WEIGHT,
                                                        algo=FLASH_ALGO),
        FlashRegion( start=0x08010000, length=0x10000,  sector_size=0x10000,
                                                        page_size=0x1000,
                                                        erase_all_weight=CHIP_ERASE_WEIGHT,
                                                        algo=FLASH_ALGO),
        FlashRegion( start=0x08020000, length=0x60000,  sector_size=0x20000,
                                                        page_size=0x1000,
                                                        erase_all_weight=CHIP_ERASE_WEIGHT,
                                                        algo=FLASH_ALGO),
        RamRegion(   start=0x20000000, length=0x40000)
        )

    def __init__(self, transport):
        super(STM32F439xG, self).__init__(transport, self.memoryMap)
        self._svd_location = SVDFile.from_builtin("STM32F439x.svd")
        
    def create_init_sequence(self):
        seq = super(STM32F439xG, self).create_init_sequence()

        seq.insert_after('create_cores',
            ('setup_dbgmcu', self.setup_dbgmcu)
            )

        return seq

    def setup_dbgmcu(self):

def __init__(self, start=0, end=0, length=None, **attrs):
        attrs['type'] = MemoryType.RAM
        super(RamRegion, self).__init__(start=start, end=end, length=length, **attrs)

self._svd_location = SVDFile.from_builtin("MIMXRT1052.xml")

class MIMXRT1052xxxxB_quadspi(CoreSightTarget):

    VENDOR = "NXP"
    
    # Note: itcm, dtcm, and ocram share a single 512 KB block of RAM that can be configurably
    # divided between those regions (this is called FlexRAM). Thus, the memory map regions for
    # each of these RAMs allocate the maximum possible of 512 KB, but that is the maximum and
    # will not actually be available in all regions simultaneously.
    memoryMap = MemoryMap(
        RamRegion(name="itcm",              start=0x00000000, length=0x80000), # 512 KB
        RomRegion(name="romcp",             start=0x00200000, length=0x18000), # 96 KB
        RomRegion(name="flexspi_alias",     start=0x08000000, length=0x8000000, alias='flexspi'), # 128 MB
        RamRegion(name="semc_alias",        start=0x10000000, length=0x10000000, alias='semc'), # 256 MB
        RamRegion(name="dtcm",              start=0x20000000, length=0x80000), # 512 KB
        RamRegion(name="ocram",             start=0x20200000, length=0x80000), # 512 KB
        FlashRegion(name="flexspi",         start=0x60000000, length=0x1f800000, blocksize=0x1000,
            is_boot_memory=True, algo=FLASH_ALGO_QUADSPI, page_size=0x100),
        RamRegion(name="semc",              start=0x80000000, end=0xdfffffff, is_external=True)
        )

    def __init__(self, link):
        super(MIMXRT1052xxxxB_quadspi, self).__init__(link, self.memoryMap)
        self._svd_location = SVDFile.from_builtin("MIMXRT1052.xml")

)

    def __init__(self, link):
        super(MIMXRT1052xxxxB_hyperflash, self).__init__(link, self.memoryMap)
        self._svd_location = SVDFile.from_builtin("MIMXRT1052.xml")

class MIMXRT1052xxxxB_quadspi(CoreSightTarget):

    VENDOR = "NXP"
    
    # Note: itcm, dtcm, and ocram share a single 512 KB block of RAM that can be configurably
    # divided between those regions (this is called FlexRAM). Thus, the memory map regions for
    # each of these RAMs allocate the maximum possible of 512 KB, but that is the maximum and
    # will not actually be available in all regions simultaneously.
    memoryMap = MemoryMap(
        RamRegion(name="itcm",              start=0x00000000, length=0x80000), # 512 KB
        RomRegion(name="romcp",             start=0x00200000, length=0x18000), # 96 KB
        RomRegion(name="flexspi_alias",     start=0x08000000, length=0x8000000, alias='flexspi'), # 128 MB
        RamRegion(name="semc_alias",        start=0x10000000, length=0x10000000, alias='semc'), # 256 MB
        RamRegion(name="dtcm",              start=0x20000000, length=0x80000), # 512 KB
        RamRegion(name="ocram",             start=0x20200000, length=0x80000), # 512 KB
        FlashRegion(name="flexspi",         start=0x60000000, length=0x1f800000, blocksize=0x1000,
            is_boot_memory=True, algo=FLASH_ALGO_QUADSPI, page_size=0x100),
        RamRegion(name="semc",              start=0x80000000, end=0xdfffffff, is_external=True)
        )

    def __init__(self, link):
        super(MIMXRT1052xxxxB_quadspi, self).__init__(link, self.memoryMap)
        self._svd_location = SVDFile.from_builtin("MIMXRT1052.xml")

'static_base' : 0x20000000 + 0x00000020 + 0x0000046c,
    'begin_stack' : 0x20000000 + 0x00000800,
    'begin_data' : 0x20000000 + 0x00000A00,
    'analyzer_supported' : True,
    'analyzer_address' : 0x1ffff000,  # Analyzer 0x1ffff000..0x1ffff600
    'page_buffers' : [0x20003000, 0x20004000],   # Enable double buffering
    'min_program_length' : 8,
  }

class K28F15(Kinetis):

    memoryMap = MemoryMap(
        FlashRegion(    start=0,           length=0x200000,     blocksize=0x1000, is_boot_memory=True,
            algo=FLASH_ALGO, flash_class=Flash_Kinetis),
        RamRegion(      start=0x1ffC0000,  length=0x80000),
        RamRegion(      start=0x34000000,  length=0x80000),
        RamRegion(      start=0x14000000,  length=0x1000)
        )

    def __init__(self, transport):
        super(K28F15, self).__init__(transport, self.memoryMap)
        self._svd_location = SVDFile.from_builtin("MK28FA15.xml")

FLASH_INT_STATUS        = 0x00034FE0
FLASH_INT_CLR_STATUS    = 0x00034FE8
FLASH_CMD_READ_SINGLE_WORD = 0x3

BOOTROM_MAGIC_ADDR      = 0x50000040

class LPC55S69JBD100(CoreSightTarget):

    memoryMap = MemoryMap(
        FlashRegion(name='nsflash',     start=0x00000000, length=0x00098000, access='rx',
            blocksize=0x200,
            is_boot_memory=True,
            are_erased_sectors_readable=False,
            algo=FLASH_ALGO),
        RomRegion(  name='nsrom',       start=0x03000000, length=0x00020000, access='rx'),
        RamRegion(  name='nscoderam',   start=0x04000000, length=0x00008000, access='rwx'),
        FlashRegion(name='sflash',      start=0x10000000, length=0x00098000, access='rx',
            blocksize=0x200,
            is_boot_memory=True,
            are_erased_sectors_readable=False,
            algo=FLASH_ALGO,
            alias='nsflash'),
        RomRegion(  name='srom',        start=0x13000000, length=0x00020000, access='srx',
            alias='nsrom'),
        RamRegion(  name='scoderam',    start=0x14000000, length=0x00008000, access='srwx',
            alias='nscoderam'),
        RamRegion(  name='nsram',       start=0x20000000, length=0x00044000, access='rwx'),
        RamRegion(  name='sram',        start=0x30000000, length=0x00044000, access='srwx',
            alias='nsram'),
        )

    def __init__(self, link):

# All keys above are auto-generated. The following are added or modified.
    'analyzer_supported' : True,                 # [modified] default is False
    'analyzer_address' : 0x1fffa000,             # [modified] default is zero. Use 8K block before flash algo. Can be any unused SRAM.
    'page_buffers' : [0x20000a00, 0x20001200],   # [added] Use areas above algo. Note 'begin_data' is unused if double buffering. Can be any unused SRAM.
    'min_program_length' : 4                     # [added] See FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE in KSDK features header file
}

class KL82Z7(Kinetis):

    memoryMap = MemoryMap(
        FlashRegion(    start=0,           length=0x20000,      blocksize=0x800, is_boot_memory=True,
            algo=FLASH_ALGO, flash_class=Flash_Kinetis),
        RomRegion(      start=0x1c000000,  end=0x1c007fff),
        RomRegion(      start=0x68000000,  end=0x6fffffff),
        RamRegion(      start=0x1fffA000,  length=0x18000)
        )

    def __init__(self, link):
        super(KL82Z7, self).__init__(link, self.memoryMap)
        self._svd_location = SVDFile.from_builtin("MKL82Z7.svd")

'static_base' : 0x20000000 + 0x00000020 + 0x0000046c,
    'begin_stack' : 0x20000000 + 0x00000800,
    'begin_data' : 0x20000000 + 0x00000A00,
    'analyzer_supported' : True,
    'analyzer_address' : 0x1ffff000,  # Analyzer 0x1ffff000..0x1ffff600
    'page_buffers' : [0x20003000, 0x20004000],   # Enable double buffering
    'min_program_length' : 8,
  }

class K66F18(Kinetis):

    memoryMap = MemoryMap(
        FlashRegion(    start=0,           length=0x200000,     blocksize=0x1000, is_boot_memory=True,
            algo=FLASH_ALGO, flash_class=Flash_Kinetis),
        RamRegion(      start=0x1fff0000,  length=0x40000),
        RamRegion(      start=0x14000000,  length=0x1000)
        )

    def __init__(self, transport):
        super(K66F18, self).__init__(transport, self.memoryMap)
        self._svd_location = SVDFile.from_builtin("MK66F18.svd")

'static_base' : 0x200001dc,
    'page_size' : 0x00000100,
    'min_program_length' : 256,
    'analyzer_supported' : False
}

class LPC54608(CoreSightTarget):

    VENDOR = "NXP"
    
    memoryMap = MemoryMap(
        FlashRegion(name='flash',   start=0,           length=0x80000,  is_boot_memory=True,
                                                                        blocksize=0x8000,
                                                                        page_size=0x100,
                                                                        algo=FLASH_ALGO),
        RamRegion(  name='sramx',   start=0x04000000,  length=0x8000),
        RamRegion(  name='sram0',   start=0x20000000,  length=0x10000),
        RamRegion(  name='sram1',   start=0x20010000,  length=0x10000),
        RamRegion(  name='sram2',   start=0x20020000,  length=0x8000)
        )

    def __init__(self, link):
        super(LPC54608, self).__init__(link, self.memoryMap)
        self.ignoreReset = False
        self._svd_location = SVDFile.from_builtin("LPC54608.xml")

    def reset_and_halt(self, reset_type=None, map_to_user=True):
        super(LPC54608, self).reset_and_halt(reset_type)

        # Remap to use flash and set SP and SP accordingly
        if map_to_user:
            self.write_memory(0x40000000, 0x2, 32)