How to use the fusesoc.utils function in fusesoc

def patch(self, dst_dir):
        #FIXME: Use native python patch instead
        patches = self.provider.patches
        for f in patches:
            patch_file = os.path.abspath(os.path.join(self.core_root, f))
            if os.path.isfile(patch_file):
                self._debug("  applying patch file: " + patch_file + "\n" +
                             "                   to: " + os.path.join(dst_dir))
                try:
                    utils.Launcher('git', ['apply', '--unsafe-paths',
                                     '--directory', os.path.join(dst_dir),
                                     patch_file]).run()
                except OSError:
                    print("Error: Failed to call external command 'patch'")
                    return False
        return True

def pgm(self, remaining):
        args = ['--mode=jtag']
        args += remaining
        args += ['-o']
        args += ['p;' + self.system.sanitized_name + '.sof']
        utils.Launcher('quartus_pgm', args, cwd=self.work_root).run()

_type = 'SYSTEMVERILOG_FILE'
            elif f.file_type in ['vhdlSource',
                                 'vhdlSource-87',
                                 'vhdlSource-93',
                                 'vhdlSource-2008']:
                _type = 'VHDL_FILE'
            elif f.file_type in ['QIP']:
                _type = 'QIP_FILE'
            elif f.file_type in ['SDC']:
                _type = 'SDC_FILE'
            elif f.file_type in ['user']:
                _type = None
            else:
                _type = None
                _s = "{} has unknown file type '{}'"
                utils.pr_warn(_s.format(f.name,
                                  f.file_type))
            if _type:
                _s = "set_global_assignment -name {} {}\n"
                tcl_file.write(_s.format(_type,
                                         f.name))

        for include_dir in incdirs:
            tcl_file.write("set_global_assignment -name SEARCH_PATH " + include_dir + '\n')

        for f in self.backend.sdc_files:
            dst_dir = os.path.join(self.src_root, self.system.sanitized_name)
            sdc_file = os.path.relpath(os.path.join(dst_dir, f.name) , self.work_root)
            tcl_file.write("set_global_assignment -name SDC_FILE " + sdc_file + '\n')

        # NOTE: The relative path _have_ to be used here, if the absolute path
        # is used, quartus_asm will fail with an error message that

f.write(''.join(['-D{}={}\n'.format(key, value) for key, value in self.vlogdefine.items()]))

        with open(os.path.join(self.work_root, 'Makefile'), 'w') as makefile:
            makefile.write(MAKEFILE_TEMPLATE)

        with open(os.path.join(self.work_root, 'config.mk'), 'w') as config_mk:
            config_mk.write(CONFIG_MK_TEMPLATE.format(
                top_module        = self.top_module,
                vc_file           = self.verilator_file,
                verilator_options = ' '.join(self.system.verilator.verilator_options)))

        #convert verilog defines into C file
        for f in self.system.verilator.define_files:
            read_file = os.path.join(self._basepath(self.system), f)
            write_file = os.path.splitext(read_file)+'.h'
            utils.convert_V2H(read_file, write_file)

def build(self, args):
        super(Icestorm, self).build(args)

        utils.Launcher('make', cwd = self.work_root).run()

        super(Icestorm, self).done()

self.include_dirs = []
        self.tb_include_dirs = []

        self._add_member('src_files'           , FileList, "Verilog source files for synthesis/simulation")
        self._add_member('include_files'       , FileList, "Verilog include files")
        self._add_member('tb_src_files'        , FileList, "Verilog source files that are only used in simulation. Visible to other cores")
        self._add_member('tb_private_src_files', FileList, "Verilog source files that are only used in the core's own testbench. Not visible to other cores")
        self._add_member('tb_include_files'    , FileList, "Testbench include files")
        self._add_member('file_type'           , str     , "Default file type of the files in fileset")

        if items:
            self.load_dict(items)
            if not self.file_type:
                self.file_type = "verilogSource"
            if self.include_files:
                self.include_dirs  += utils.unique_dirs(self.include_files)
            if self.tb_include_files:
                self.tb_include_dirs  += utils.unique_dirs(self.tb_include_files)

            self.export_files = self.src_files + self.include_files + self.tb_src_files + self.tb_include_files + self.tb_private_src_files

def pgm(self, remaining):
        pgm_file_name = os.path.join(self.work_root, self.system.sanitized_name+'.pgm')
        self._write_pgm_file(pgm_file_name)
        utils.Launcher('impact', ['-batch', pgm_file_name],
                           cwd = self.work_root,
                           errormsg = "impact tool returned an error").run()