How to use the fusesoc.capi1.section.Section function in fusesoc

self._add_member('quartus_options', str, 'Quartus command-line options')
        self._add_member('family'         , str, 'FPGA device family')
        self._add_member('device'         , str, 'FPGA device identifier')
        self._add_member('top_module'     , str, 'RTL top-level module')

        self.top_module = 'orpsoc_top'
        if items:
            self.load_dict(items)

    def __str__(self):
        s = ''
        for x in ['family', 'device', 'top_module']:
            s += "{} : {}\n".format(self._members[x]['desc'], getattr(self, x))
        return s

class ParameterSection(Section):
    TAG = 'parameter'
    named = True
    def __init__(self, items=None):
        super(ParameterSection, self).__init__()

        self._add_member('datatype'   , str, 'Data type of argument (int, str, bool, file')
        self._add_member('default'    , str, 'Default value of argument')
        self._add_member('description', str, 'Parameter description')
        self._add_member('paramtype'  , str, 'Type of parameter (plusarg, vlogparam, generic, cmdlinearg')
        self._add_member('scope'      , str, 'Visibility of parameter. Private parameters are only visible when this core is the top-level. Public parameters are visible also when this core is pulled in as a dependency of another core')

        if items:
            self.load_dict(items)
            if not self.datatype in ['bool', 'file', 'int', 'str']:
                _s = "Invalid datatype '{}' for parameter"
                raise SyntaxError(_s.format(self.datatype))

return s

class ScriptsSection(Section):
    TAG = 'scripts'
    def __init__(self, items=None):
        super(ScriptsSection, self).__init__()
        self._add_member('pre_synth_scripts', StringList, 'Scripts to run before backend synthesis')
        self._add_member('post_impl_scripts', StringList, 'Scripts to run after backend implementation')
        self._add_member('pre_build_scripts', StringList, 'Scripts to run before building')
        self._add_member('pre_run_scripts'  , StringList, 'Scripts to run before running simulations')
        self._add_member('post_run_scripts' , StringList, 'Scripts to run after simulations')

        if items:
            self.load_dict(items)

class ToolSection(Section):
    def __init__(self):
        super(ToolSection, self).__init__()
        self._add_member('depend', VlnvList, "Tool-specific Dependencies")
    def __str__(self):
        s = ""
        if self.depend:
            _s = "{}-specific dependencies : {}\n"
            s += _s.format(self.TAG,
                     ' '.join([x.depstr() for x in self.depend]))
        return(s)

class MainSection(Section):
    TAG = 'main'

    def __init__(self, items=None):
        super(MainSection, self).__init__()

self._add_member('tb_private_src_files', FileList, "Verilog source files that are only used in the core's own testbench. Not visible to other cores")
        self._add_member('tb_include_files'    , FileList, "Testbench include files")
        self._add_member('file_type'           , str     , "Default file type of the files in fileset")

        if items:
            self.load_dict(items)
            if not self.file_type:
                self.file_type = "verilogSource"
            if self.include_files:
                self.include_dirs  += unique_dirs(self.include_files)
            if self.tb_include_files:
                self.tb_include_dirs  += unique_dirs(self.tb_include_files)

            self.export_files = self.src_files + self.include_files + self.tb_src_files + self.tb_include_files + self.tb_private_src_files

class FileSetSection(Section):
    TAG = 'fileset'
    named = True
    def __init__(self, items=None):
        super(FileSetSection, self).__init__()

        self._add_member('files'          , FileList, "List of files in fileset")
        self._add_member('file_type'      , str     , "Default file type of the files in fileset")
        self._add_member('is_include_file', str     , "Specify all files in fileset as include files")
        self._add_member('logical_name'   , str     , "Default logical_name (e.g. library) of the files in fileset")
        self._add_member('scope'          , str     , "Visibility of fileset (private/public). Private filesets are only visible when this core is the top-level. Public filesets are visible also for cores that depend on this core. Default is public")
        self._add_member('usage'          , StringList, "List of tags describing when this fileset should be used. Can be general such as sim or synth, or tool-specific such as quartus, verilator, icarus. Defaults to 'sim synth'.")
        if items:
            self.load_dict(items)
            if not self.scope:
                self.scope = 'public'
            if not self.usage:

def __init__(self, items=None):
        super(MainSection, self).__init__()

        self._add_member('name'       , str     , "Component name")
        self._add_member('backend'    , str     , "Backend for FPGA implementation")
        self._add_member('component'  , PathList, "Core IP-Xact component file")
        self._add_member('description', str, "Core description")
        self._add_member('depend'     , VlnvList, "Common dependencies")
        self._add_member('simulators' , SimulatorList, "Supported simulators. Valid values are icarus, modelsim, verilator, isim and xsim. Each simulator have a dedicated section desribed elsewhere in this document")
        self._add_member('patches'    , StringList, "FuseSoC-specific patches")

        if items:
            self.load_dict(items)

class VhdlSection(Section):

    TAG = 'vhdl'

    def __init__(self, items=None):
        super(VhdlSection, self).__init__()

        self._add_member('src_files', PathList, "VHDL source files for simulation and synthesis")

        if items:
            self.load_dict(items)
            self.export_files = self.src_files

class VerilogSection(Section):

    TAG = 'verilog'

self.load_dict(items)

class VhdlSection(Section):

    TAG = 'vhdl'

    def __init__(self, items=None):
        super(VhdlSection, self).__init__()

        self._add_member('src_files', PathList, "VHDL source files for simulation and synthesis")

        if items:
            self.load_dict(items)
            self.export_files = self.src_files

class VerilogSection(Section):

    TAG = 'verilog'

    def __init__(self, items=None):
        super(VerilogSection, self).__init__()

        self.include_dirs = []
        self.tb_include_dirs = []

        self._add_member('src_files'           , FileList, "Verilog source files for synthesis/simulation")
        self._add_member('include_files'       , FileList, "Verilog include files")
        self._add_member('tb_src_files'        , FileList, "Verilog source files that are only used in simulation. Visible to other cores")
        self._add_member('tb_private_src_files', FileList, "Verilog source files that are only used in the core's own testbench. Not visible to other cores")
        self._add_member('tb_include_files'    , FileList, "Testbench include files")
        self._add_member('file_type'           , str     , "Default file type of the files in fileset")

self.load_dict(items)
            if not self.scope:
                self.scope = 'public'
            if not self.usage:
                self.usage = ['sim', 'synth']
            for f in self.files:
                if not f.file_type:
                    f.file_type = self.file_type
                if self.is_include_file.lower() == "true":
                    f.is_include_file = True
                if not f.logical_name:
                    f.logical_name = self.logical_name
            self.export_files = self.files


class VpiSection(Section):

    TAG = 'vpi'

    def __init__(self, items=None):
        super(VpiSection, self).__init__()

        self.include_dirs = []

        self._add_member('src_files'    , FileList, "C source files for VPI library")
        self._add_member('include_files', FileList, "C include files for VPI library")
        self._add_member('libs'         , StringList, "External libraries linked with the VPI library")

        if items:
            self.load_dict(items)
            if self.include_files:
                self.include_dirs  += unique_dirs(self.include_files)

if items:
            self.load_dict(items)

class ToolSection(Section):
    def __init__(self):
        super(ToolSection, self).__init__()
        self._add_member('depend', VlnvList, "Tool-specific Dependencies")
    def __str__(self):
        s = ""
        if self.depend:
            _s = "{}-specific dependencies : {}\n"
            s += _s.format(self.TAG,
                     ' '.join([x.depstr() for x in self.depend]))
        return(s)

class MainSection(Section):
    TAG = 'main'

    def __init__(self, items=None):
        super(MainSection, self).__init__()

        self._add_member('name'       , str     , "Component name")
        self._add_member('backend'    , str     , "Backend for FPGA implementation")
        self._add_member('component'  , PathList, "Core IP-Xact component file")
        self._add_member('description', str, "Core description")
        self._add_member('depend'     , VlnvList, "Common dependencies")
        self._add_member('simulators' , SimulatorList, "Supported simulators. Valid values are icarus, modelsim, verilator, isim and xsim. Each simulator have a dedicated section desribed elsewhere in this document")
        self._add_member('patches'    , StringList, "FuseSoC-specific patches")

        if items:
            self.load_dict(items)

setattr(self, item, _type(e.args[0]))
            else:
                self.warnings.append(
                        'Unknown item "%(item)s" in section "%(section)s"' % {
                            'item': item, 'section': self.TAG})

    def __str__(self):
        s = ''
        for k,v in self._members.items():
            if isinstance(v.get('type'), list):
                s += k + ' : ' + ';'.join(getattr(self, item)) + '\n'
            elif isinstance(v.get('type'), str):
                s += k + ' : ' + getattr(self, k) + '\n'
        return s

class ScriptsSection(Section):
    TAG = 'scripts'
    def __init__(self, items=None):
        super(ScriptsSection, self).__init__()
        self._add_member('pre_synth_scripts', StringList, 'Scripts to run before backend synthesis')
        self._add_member('post_impl_scripts', StringList, 'Scripts to run after backend implementation')
        self._add_member('pre_build_scripts', StringList, 'Scripts to run before building')
        self._add_member('pre_run_scripts'  , StringList, 'Scripts to run before running simulations')
        self._add_member('post_run_scripts' , StringList, 'Scripts to run after simulations')

        if items:
            self.load_dict(items)

class ToolSection(Section):
    def __init__(self):
        super(ToolSection, self).__init__()
        self._add_member('depend', VlnvList, "Tool-specific Dependencies")

if section:
            yield section


SECTION_MAP = {}


def _register_subclasses(parent):
    for cls in parent.__subclasses__():
        _register_subclasses(cls)
        if cls.TAG is None:
            continue
        SECTION_MAP[cls.TAG] = cls


_register_subclasses(Section)

if __name__ == "__main__":
    FILE_TEMPLATE = """CAPI1 Definition
===============
:toc:

Type definitions
----------------
{types}

[[FileTypes]]
File types
----------

The following valid file types are defined: {filetypes}