How to use the fusesoc.core.Core function in fusesoc

def test_core_info():
    tests_dir = os.path.dirname(__file__)
    cores_root = os.path.join(tests_dir, 'cores')
    for core_name in ['sockit', 'mor1kx-generic']:
        core = Core(os.path.join(cores_root, core_name, core_name+'.core'))
        gen_info = '\n'.join([x for x in core.info().split('\n') if not 'Core root' in x])
        with open(os.path.join(tests_dir, __name__, core_name+".info")) as f:
            assert f.read() == gen_info, core_name

def test_capi2_export():
    import os
    import tempfile
    from fusesoc.core import Core

    core_file = os.path.join(tests_dir,
                             "capi2_cores",
                             "misc",
                             "files.core")
    core = Core(core_file)

    export_root  = tempfile.mkdtemp(prefix='capi2_export_')

    core.export(export_root)

    expected = [
        'dontpickthisfile',
        'dummy.tcl',
        'scriptfile',
        'subdir/dummy.extra',
        'vhdlfile',
        'vlogfile',
        'vpifile']
    result = []

    for root, dirs, files in os.walk(export_root):

def test_ise():
    filename = os.path.join(os.path.dirname(__file__),
                            __name__,
                            "atlys.core")
    core = Core(filename)

    #Check filesets
    assert len(core.file_sets) == 4
    assert core.file_sets[0].name == 'verilog_src_files'
    assert core.file_sets[1].name == 'verilog_tb_src_files'
    assert core.file_sets[2].name == 'verilog_tb_private_src_files'

    #Check that backend files are converted to fileset properly
    compare_fileset(core.file_sets[3], 'backend_files', ['data/atlys.ucf'])
    assert core.file_sets[3].file[0].file_type == 'UCF'

    #Check backend section
    assert core.ise.export_files == []
    assert core.ise.family == 'spartan6'
    assert core.ise.device == 'xc6slx45'
    assert core.ise.package == 'csg324'

def test_simulator():
    #Explicit toplevel
    filename = os.path.join(os.path.dirname(__file__),
                            __name__,
                            "c3demo.core")
    core = Core(filename)
    assert core.simulator['toplevel'] == 'testbench'

    #Implicit toplevel
    filename = os.path.join(os.path.dirname(__file__),
                            __name__,
                            "atlys.core")
    core = Core(filename)
    assert core.simulator['toplevel'] == 'orpsoc_tb'

def test_logicore_provider():

    cache_root = tempfile.mkdtemp('logicore_')
    core = Core(os.path.join(cores_root, 'misc', 'logicorecore.core'), cache_root)

    os.environ['PATH'] = os.path.join(tests_dir, 'mock_commands')+':'+os.environ['PATH']
    core.setup()

    for f in ['dummy.tcl',
	      'dummy.xci',
	      os.path.join('subdir', 'dummy.extra')]:
        assert(os.path.isfile(os.path.join(core.files_root, f)))

    with open(os.path.join(core.files_root, 'vivado.cmd')) as f:
        assert(f.read() == '-mode batch -source dummy.tcl\n')

def test_get_tool_options():
    cores_root = os.path.join(os.path.dirname(__file__), 'cores')

    core = Core(os.path.join(cores_root, 'mor1kx-generic', 'mor1kx-generic.core'))
    assert {'iverilog_options' : ['-DSIM']} == core.get_tool_options({'is_toplevel' : True, 'tool' : 'icarus'})
    assert {} == core.get_tool_options({'is_toplevel' : True, 'tool' : 'modelsim'})
    assert {'fuse_options' : ['some','isim','options']} == core.get_tool_options({'is_toplevel' : True, 'tool' : 'isim'})
    expected = {'xelab_options' : ['--timescale 1ps/1ps', '--debug typical',
                                   'dummy', 'options', 'for', 'xelab']}
    assert expected == core.get_tool_options({'is_toplevel' : True, 'tool' : 'xsim'})
    assert {} == core.get_tool_options({'is_toplevel' : False, 'tool' : 'icarus'})

    core = Core(os.path.join(cores_root, 'elf-loader', 'elf-loader.core'))
    assert {'libs' : ['-lelf']} == core.get_tool_options({'is_toplevel' : False, 'tool' : 'verilator'})
    assert {} == core.get_tool_options({'is_toplevel' : True, 'tool' : 'invalid'})

def test_capi2_get_generators():
    from fusesoc.core import Core

    core = Core(os.path.join(cores_dir, "generators.core"))

    generators = core.get_generators({})
    assert len(generators) == 1
    assert generators['generator1'].command == 'testgen.py'

def test_git_provider():
    cache_root = tempfile.mkdtemp('git_')
    core = Core(os.path.join(cores_root, 'misc', 'gitcore.core'), cache_root)
    
    core.setup()

    for f in ['LICENSE',
	      'README.md',
	      'wb_common.core',
	      'wb_common.v',
	      'wb_common_params.v']:
        assert(os.path.isfile(os.path.join(core.files_root, f)))

def test_get_toplevel():
    filename = os.path.join(os.path.dirname(__file__),
                            __name__,
                            "atlys.core")
    core = Core(filename)
    assert 'orpsoc_tb'  == core.get_toplevel({'tool' : 'icarus'})
    assert 'orpsoc_tb'  == core.get_toplevel({'tool' : 'icarus', 'testbench' : None})
    assert 'tb'         == core.get_toplevel({'tool' : 'icarus', 'testbench' : 'tb'})
    assert 'orpsoc_top' == core.get_toplevel({'tool' : 'vivado'})
    filename = os.path.join(os.path.dirname(__file__),
                            __name__,
                            "sockit.core")
    core = Core(filename)
    assert 'dummy_tb'   == core.get_toplevel({'tool' : 'icarus'})
    assert 'dummy_tb'   == core.get_toplevel({'tool' : 'icarus', 'testbench' : None})
    assert 'tb'         == core.get_toplevel({'tool' : 'icarus', 'testbench' : 'tb'})
    assert 'orpsoc_top' == core.get_toplevel({'tool' : 'vivado'})

def test_capi2_get_depends():
    from fusesoc.core import Core
    from fusesoc.vlnv import Vlnv

    core = Core(os.path.join(tests_dir,
                             "capi2_cores",
                             "misc",
                             "depends.core"))
    flags = {}
    result = core.get_depends(flags)

    expected = [
        Vlnv('unversioned'),
        Vlnv('versioned-1.0'),
        Vlnv('gt-1.0'),
        Vlnv('>=gte-1.0'),
        Vlnv('::n'),
        Vlnv('::nv:1.0'),