How to use the fusesoc.capi1.section.ToolSection function in fusesoc

self.load_dict(items)
            self.include_dirs  = unique_dirs(self.include_files)
            if not self.source_type:
                self.source_type = 'C'

    def __str__(self):
        s = super(VerilatorSection, self).__str__()
        s += """Verilator options       : {verilator_options}
External libraries      : {libs}
Verilog top module      : {top_module}
"""
        return s.format(verilator_options=' '.join(self.verilator_options),
                        libs=' '.join(self.libs),
                        top_module=self.top_module)

class IcestormSection(ToolSection):

    TAG = 'icestorm'

    def __init__(self, items=None):
        super(IcestormSection, self).__init__()

        self._add_member('arachne_pnr_options', StringList, "arachne-pnr options")
        self._add_member('yosys_synth_options' , StringList, "Additional options for the synth_* commands in yosys")
        self._add_member('pcf_file' , FileList, "Physical constraint file")
        self._add_member('top_module', str, 'RTL top-level module')

        if items:
            self.load_dict(items)

class TrellisSection(ToolSection):

self.load_dict(items)

class RivieraproSection(ToolSection):

    TAG = 'rivierapro'

    def __init__(self, items=None):
        super(RivieraproSection, self).__init__()

        self._add_member('vlog_options', StringList, "Additional arguments for vlog")
        self._add_member('vsim_options', StringList, "Additional arguments for vsim")

        if items:
            self.load_dict(items)

class GhdlSection(ToolSection):
    TAG = 'ghdl'

    def __init__(self, items=None):
        super(GhdlSection, self).__init__()

        self._add_member('analyze_options', StringList, "Extra GHDL analyzer options")
        self._add_member('run_options', StringList, "Extra GHDL run options")

        if items:
            self.load_dict(items)

    def __str__(self):
        s = super(GhdlSection, self).__str__()
        if self.analyze_options: s += "Extra GHDL analyzer options : {}\n".format(' '.join(self.analyze_options))
        if self.run_options: s += "Extra GHDL run options : {}\n".format(' '.join(self.run_options))
        return s

def __init__(self, items=None):
        super(IsimSection, self).__init__()

        self._add_member('isim_options', StringList, "Extra Isim compile options")

        if items:
            self.load_dict(items)

    def __str__(self):
        s = super(IsimSection, self).__str__()
        if self.isim_options: s += "Isim compile options : {}\n".format(' '.join(self.isim_options))
        return s


class XsimSection(ToolSection):

    TAG = 'xsim'

    def __init__(self, items=None):
        super(XsimSection, self).__init__()

        self._add_member('xsim_options', StringList, "Extra Xsim compile options")

        if items:
            self.load_dict(items)

    def __str__(self):
        s = super(XsimSection, self).__str__()
        if self.xsim_options: s += "Xsim compile options : {}\n".format(' '.join(self.xsim_options))
        return s

def __init__(self, items=None):
        super(GhdlSection, self).__init__()

        self._add_member('analyze_options', StringList, "Extra GHDL analyzer options")
        self._add_member('run_options', StringList, "Extra GHDL run options")

        if items:
            self.load_dict(items)

    def __str__(self):
        s = super(GhdlSection, self).__str__()
        if self.analyze_options: s += "Extra GHDL analyzer options : {}\n".format(' '.join(self.analyze_options))
        if self.run_options: s += "Extra GHDL run options : {}\n".format(' '.join(self.run_options))
        return s

class IcarusSection(ToolSection):

    TAG = 'icarus'

    def __init__(self, items=None):
        super(IcarusSection, self).__init__()

        self._add_member('iverilog_options', StringList, "Extra Icarus verilog compile options")

        if items:
            self.load_dict(items)

    def __str__(self):
        s = super(IcarusSection, self).__str__()
        if self.iverilog_options: s += "Icarus compile options : {}\n".format(' '.join(self.iverilog_options))
        return s

class IcestormSection(ToolSection):

    TAG = 'icestorm'

    def __init__(self, items=None):
        super(IcestormSection, self).__init__()

        self._add_member('arachne_pnr_options', StringList, "arachne-pnr options")
        self._add_member('yosys_synth_options' , StringList, "Additional options for the synth_* commands in yosys")
        self._add_member('pcf_file' , FileList, "Physical constraint file")
        self._add_member('top_module', str, 'RTL top-level module')

        if items:
            self.load_dict(items)

class TrellisSection(ToolSection):

    TAG = 'trellis'

    def __init__(self, items=None):
        super(TrellisSection, self).__init__()

        self._add_member('nextpnr_options', StringList, "nextpnr options")
        self._add_member('yosys_synth_options' , StringList, "Additional options for the synth_* commands in yosys")
        self._add_member('top_module', str, 'RTL top-level module')

        if items:
            self.load_dict(items)

class VivadoSection(ToolSection):

    TAG = 'vivado'

def __init__(self):
        super(ToolSection, self).__init__()
        self._add_member('depend', VlnvList, "Tool-specific Dependencies")
    def __str__(self):

class VivadoSection(ToolSection):

    TAG = 'vivado'

    def __init__(self, items=None):
        super(VivadoSection, self).__init__()

        self._add_member('part'       , str, 'FPGA device part')
        self._add_member('hw_device'  , str, 'FPGA device identifier')
        self._add_member('top_module' , str, 'RTL top-level module')

        if items:
            self.load_dict(items)

class IseSection(ToolSection):

    TAG = 'ise'

    def __init__(self, items=None):
        super(IseSection, self).__init__()

        self._add_member('ucf_files' , FileList, "UCF constraint files")
        self._add_member('tcl_files' , FileList, "Extra TCL scripts")
        self._add_member('family'    , str, 'FPGA device family')
        self._add_member('device'    , str, 'FPGA device identifier')
        self._add_member('package'   , str, 'FPGA device package')
        self._add_member('speed'     , str, 'FPGA device speed grade')
        self._add_member('top_module', str, 'RTL top-level module')

        if items:
            self.load_dict(items)

TAG = 'xsim'

    def __init__(self, items=None):
        super(XsimSection, self).__init__()

        self._add_member('xsim_options', StringList, "Extra Xsim compile options")

        if items:
            self.load_dict(items)

    def __str__(self):
        s = super(XsimSection, self).__str__()
        if self.xsim_options: s += "Xsim compile options : {}\n".format(' '.join(self.xsim_options))
        return s

class VcsSection(ToolSection):

    TAG = 'vcs'

    def __init__(self, items=None):
        super(VcsSection, self).__init__()

        self._add_member('vcs_options', StringList, "Extra vcs compile options")

        if items:
            self.load_dict(items)

    def __str__(self):
        s = super(VcsSection, self).__str__()
        if self.vcs_options: s += "Vcs compile options : {}\n".format(' '.join(self.vcs_options))
        return s

TAG = 'vcs'

    def __init__(self, items=None):
        super(VcsSection, self).__init__()

        self._add_member('vcs_options', StringList, "Extra vcs compile options")

        if items:
            self.load_dict(items)

    def __str__(self):
        s = super(VcsSection, self).__str__()
        if self.vcs_options: s += "Vcs compile options : {}\n".format(' '.join(self.vcs_options))
        return s

class VerilatorSection(ToolSection):

    TAG = 'verilator'

    def __init__(self, items=None):
        super(VerilatorSection, self).__init__()

        self.include_dirs = []

        self._add_member('verilator_options', StringList, "Verilator build options")
        self._add_member('src_files'        , FileList  , "Verilator testbench C/cpp/sysC source files")
        self._add_member('include_files'    , FileList  , "Verilator testbench C include files")
        self._add_member('define_files'     , PathList  , "Verilog include files containing `define directives to be converted to C #define directives in corresponding .h files (deprecated)")
        self._add_member('libs'             , PathList  , "External libraries linked with the generated model")

        self._add_member('tb_toplevel', FileList, 'Testbench top-level C/C++/SC file')
        self._add_member('source_type', str, 'Testbench source code language (Legal values are systemC, C, CPP. Default is C)')

class ModelsimSection(ToolSection):

    TAG = 'modelsim'

    def __init__(self, items=None):
        super(ModelsimSection, self).__init__()

        self._add_member('vlog_options', StringList, "Additional arguments for vlog")
        self._add_member('vsim_options', StringList, "Additional arguments for vsim")

        if items:
            self.load_dict(items)

class RivieraproSection(ToolSection):

    TAG = 'rivierapro'

    def __init__(self, items=None):
        super(RivieraproSection, self).__init__()

        self._add_member('vlog_options', StringList, "Additional arguments for vlog")
        self._add_member('vsim_options', StringList, "Additional arguments for vsim")

        if items:
            self.load_dict(items)

class GhdlSection(ToolSection):
    TAG = 'ghdl'

    def __init__(self, items=None):