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How to use the unicorn.arm_const function in unicorn

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github cea-sec / Sibyl / sibyl / engine / qemu.py View on Github external
def __init__(self, *args, **kwargs):
        import unicorn.arm_const as csts
        self.regs = {
            'CPSR': csts.UC_ARM_REG_CPSR, 'SPSR': csts.UC_ARM_REG_SPSR,
            'R4': csts.UC_ARM_REG_R4, 'R5': csts.UC_ARM_REG_R5,
            'R6': csts.UC_ARM_REG_R6, 'R1': csts.UC_ARM_REG_R1,
            'R7': csts.UC_ARM_REG_R7, 'R0': csts.UC_ARM_REG_R0,
            'R2': csts.UC_ARM_REG_R2, 'R3': csts.UC_ARM_REG_R3,
            'R8': csts.UC_ARM_REG_R8, 'R15': csts.UC_ARM_REG_R15,
            'R9': csts.UC_ARM_REG_R9, 'R14': csts.UC_ARM_REG_R14,
            'R12': csts.UC_ARM_REG_R12, 'R13': csts.UC_ARM_REG_R13,
            'R10': csts.UC_ARM_REG_R10, 'SL': csts.UC_ARM_REG_SL,
            'R11': csts.UC_ARM_REG_R11, 'SP': csts.UC_ARM_REG_SP,
            'SB': csts.UC_ARM_REG_SB, 'LR': csts.UC_ARM_REG_LR,
        }
        self.pc_reg_name = "PC"
        self.pc_reg_value = csts.UC_ARM_REG_PC
        super(UcWrapCPU_arml, self).__init__(*args, **kwargs)
github Ledger-Donjon / rainbow / rainbow / generics / cortexm.py View on Github external
def __init__(self, trace=True, sca_mode=False, local_vars={}):
        super().__init__(trace, sca_mode)
        self.emu = uc.Uc(uc.UC_ARCH_ARM, uc.UC_MODE_THUMB | uc.UC_MODE_MCLASS)
        self.disasm = cs.Cs(cs.CS_ARCH_ARM, cs.CS_MODE_THUMB | cs.CS_MODE_MCLASS)
        self.disasm.detail = True
        self.word_size = 4
        self.endianness = "little"
        self.page_size = self.emu.query(uc.UC_QUERY_PAGE_SIZE)
        self.page_shift = self.page_size.bit_length() - 1
        self.pc = uc.arm_const.UC_ARM_REG_PC

        known_regs = [i[len('UC_ARM_REG_'):] for i in dir(uc.arm_const) if '_REG' in i]
        self.reg_map = {r.lower(): getattr(uc.arm_const, 'UC_ARM_REG_'+r) for r in known_regs}

        self.stubbed_functions = local_vars
        self.setup(sca_mode)

        self.reset_stack()
        # Force mapping of those addresses so that
        # exception returns can be caught in the base
        # block hook rather than a code fetch hook
        self.map_space(0xfffffff0, 0xffffffff)

        self.emu.hook_add(uc.UC_HOOK_INTR, self.intr_hook)
github SimonTheCoder / pyGDB_remote / unicorn_machine.py View on Github external
def __init__(self):
        super(Unicorn_machine_arm,self).__init__(unicorn.UC_ARCH_ARM,unicorn.UC_MODE_ARM,True)
        self.mu.mem_map(0x60000000, 128*1024*1024) #ram for qemu vexpress machine, 128M
        if __DEBUG__:
            #map a test area
            self.mu.mem_map(0xfffff000, 4*1024)
        self.uc_gen_regs = [
        unicorn.arm_const.UC_ARM_REG_R0,
        unicorn.arm_const.UC_ARM_REG_R1,
        unicorn.arm_const.UC_ARM_REG_R2,
        unicorn.arm_const.UC_ARM_REG_R3,
        unicorn.arm_const.UC_ARM_REG_R4,
        unicorn.arm_const.UC_ARM_REG_R5,
        unicorn.arm_const.UC_ARM_REG_R6,
        unicorn.arm_const.UC_ARM_REG_R7,
        unicorn.arm_const.UC_ARM_REG_R8,
        unicorn.arm_const.UC_ARM_REG_R9,
        unicorn.arm_const.UC_ARM_REG_R10,
        unicorn.arm_const.UC_ARM_REG_R11,
        unicorn.arm_const.UC_ARM_REG_R12,
        unicorn.arm_const.UC_ARM_REG_R13,
        unicorn.arm_const.UC_ARM_REG_R14,
        unicorn.arm_const.UC_ARM_REG_R15
        ]

        self.uc_nzcv_reg = unicorn.arm_const.UC_ARM_REG_CPSR
        self.uc_pc_reg = unicorn.arm_const.UC_ARM_REG_R15
github SimonTheCoder / pyGDB_remote / unicorn_machine.py View on Github external
unicorn.arm_const.UC_ARM_REG_R3,
        unicorn.arm_const.UC_ARM_REG_R4,
        unicorn.arm_const.UC_ARM_REG_R5,
        unicorn.arm_const.UC_ARM_REG_R6,
        unicorn.arm_const.UC_ARM_REG_R7,
        unicorn.arm_const.UC_ARM_REG_R8,
        unicorn.arm_const.UC_ARM_REG_R9,
        unicorn.arm_const.UC_ARM_REG_R10,
        unicorn.arm_const.UC_ARM_REG_R11,
        unicorn.arm_const.UC_ARM_REG_R12,
        unicorn.arm_const.UC_ARM_REG_R13,
        unicorn.arm_const.UC_ARM_REG_R14,
        unicorn.arm_const.UC_ARM_REG_R15
        ]

        self.uc_nzcv_reg = unicorn.arm_const.UC_ARM_REG_CPSR
        self.uc_pc_reg = unicorn.arm_const.UC_ARM_REG_R15
github cea-sec / Sibyl / sibyl / engine / qemu.py View on Github external
def __init__(self, *args, **kwargs):
        import unicorn.arm_const as csts
        self.regs = {
            'CPSR': csts.UC_ARM_REG_CPSR, 'SPSR': csts.UC_ARM_REG_SPSR,
            'R4': csts.UC_ARM_REG_R4, 'R5': csts.UC_ARM_REG_R5,
            'R6': csts.UC_ARM_REG_R6, 'R1': csts.UC_ARM_REG_R1,
            'R7': csts.UC_ARM_REG_R7, 'R0': csts.UC_ARM_REG_R0,
            'R2': csts.UC_ARM_REG_R2, 'R3': csts.UC_ARM_REG_R3,
            'R8': csts.UC_ARM_REG_R8, 'R15': csts.UC_ARM_REG_R15,
            'R9': csts.UC_ARM_REG_R9, 'R14': csts.UC_ARM_REG_R14,
            'R12': csts.UC_ARM_REG_R12, 'R13': csts.UC_ARM_REG_R13,
            'R10': csts.UC_ARM_REG_R10, 'SL': csts.UC_ARM_REG_SL,
            'R11': csts.UC_ARM_REG_R11, 'SP': csts.UC_ARM_REG_SP,
            'SB': csts.UC_ARM_REG_SB, 'LR': csts.UC_ARM_REG_LR,
        }
        self.pc_reg_name = "PC"
        self.pc_reg_value = csts.UC_ARM_REG_PC
        super(UcWrapCPU_armtl, self).__init__(*args, **kwargs)
github SimonTheCoder / pyGDB_remote / unicorn_machine.py View on Github external
def __init__(self):
        super(Unicorn_machine_arm,self).__init__(unicorn.UC_ARCH_ARM,unicorn.UC_MODE_ARM,True)
        self.mu.mem_map(0x60000000, 128*1024*1024) #ram for qemu vexpress machine, 128M
        if __DEBUG__:
            #map a test area
            self.mu.mem_map(0xfffff000, 4*1024)
        self.uc_gen_regs = [
        unicorn.arm_const.UC_ARM_REG_R0,
        unicorn.arm_const.UC_ARM_REG_R1,
        unicorn.arm_const.UC_ARM_REG_R2,
        unicorn.arm_const.UC_ARM_REG_R3,
        unicorn.arm_const.UC_ARM_REG_R4,
        unicorn.arm_const.UC_ARM_REG_R5,
        unicorn.arm_const.UC_ARM_REG_R6,
        unicorn.arm_const.UC_ARM_REG_R7,
        unicorn.arm_const.UC_ARM_REG_R8,
        unicorn.arm_const.UC_ARM_REG_R9,
        unicorn.arm_const.UC_ARM_REG_R10,
        unicorn.arm_const.UC_ARM_REG_R11,
        unicorn.arm_const.UC_ARM_REG_R12,
        unicorn.arm_const.UC_ARM_REG_R13,
        unicorn.arm_const.UC_ARM_REG_R14,
        unicorn.arm_const.UC_ARM_REG_R15
        ]

        self.uc_nzcv_reg = unicorn.arm_const.UC_ARM_REG_CPSR
        self.uc_pc_reg = unicorn.arm_const.UC_ARM_REG_R15
github cea-sec / Sibyl / sibyl / engine / qemu.py View on Github external
def __init__(self, *args, **kwargs):
        import unicorn.arm_const as csts
        self.regs = {
            'CPSR': csts.UC_ARM_REG_CPSR, 'SPSR': csts.UC_ARM_REG_SPSR,
            'R4': csts.UC_ARM_REG_R4, 'R5': csts.UC_ARM_REG_R5,
            'R6': csts.UC_ARM_REG_R6, 'R1': csts.UC_ARM_REG_R1,
            'R7': csts.UC_ARM_REG_R7, 'R0': csts.UC_ARM_REG_R0,
            'R2': csts.UC_ARM_REG_R2, 'R3': csts.UC_ARM_REG_R3,
            'R8': csts.UC_ARM_REG_R8, 'R15': csts.UC_ARM_REG_R15,
            'R9': csts.UC_ARM_REG_R9, 'R14': csts.UC_ARM_REG_R14,
            'R12': csts.UC_ARM_REG_R12, 'R13': csts.UC_ARM_REG_R13,
            'R10': csts.UC_ARM_REG_R10, 'SL': csts.UC_ARM_REG_SL,
            'R11': csts.UC_ARM_REG_R11, 'SP': csts.UC_ARM_REG_SP,
            'SB': csts.UC_ARM_REG_SB, 'LR': csts.UC_ARM_REG_LR,
        }
        self.pc_reg_name = "PC"
        self.pc_reg_value = csts.UC_ARM_REG_PC
        super(UcWrapCPU_arml, self).__init__(*args, **kwargs)
github fgsect / unicorefuzz / util.py View on Github external
from unicorn.x86_const import *
from capstone import *
from capstone.x86 import *

import struct
import avatar2

import config

# TODO: fix avatar2 x86 mode
X64 = X86_64
X86.unicorn_arch = unicorn.UC_ARCH_X86
X86.unicorn_mode = unicorn.UC_MODE_32
X64.unicorn_mode = unicorn.UC_MODE_64

ARM.unicorn_consts = unicorn.arm_const
X86.unicorn_consts = unicorn.x86_const

ARM.unicorn_reg_tag = "UC_ARM_REG_"
ARM.ignored_regs = []
X86.unicorn_reg_tag = "UC_X86_REG_"
X86.ignored_regs = ["cr0","cr2","cr3","cr4","cr8"] # these make unicorn crash
#TODO: arm64, mips, etc.


FSMSR = 0xC0000100
GSMSR = 0xC0000101

MAPPED_PAGES = {}
PAGE_SIZE = 0x1000

SYSCALL_OPCODE = b'\x0f\x05'
github cea-sec / Sibyl / sibyl / engine / qemu.py View on Github external
def __init__(self, *args, **kwargs):
        import unicorn.arm_const as csts
        self.regs = {
            'CPSR': csts.UC_ARM_REG_CPSR, 'SPSR': csts.UC_ARM_REG_SPSR,
            'R4': csts.UC_ARM_REG_R4, 'R5': csts.UC_ARM_REG_R5,
            'R6': csts.UC_ARM_REG_R6, 'R1': csts.UC_ARM_REG_R1,
            'R7': csts.UC_ARM_REG_R7, 'R0': csts.UC_ARM_REG_R0,
            'R2': csts.UC_ARM_REG_R2, 'R3': csts.UC_ARM_REG_R3,
            'R8': csts.UC_ARM_REG_R8, 'R15': csts.UC_ARM_REG_R15,
            'R9': csts.UC_ARM_REG_R9, 'R14': csts.UC_ARM_REG_R14,
            'R12': csts.UC_ARM_REG_R12, 'R13': csts.UC_ARM_REG_R13,
            'R10': csts.UC_ARM_REG_R10, 'SL': csts.UC_ARM_REG_SL,
            'R11': csts.UC_ARM_REG_R11, 'SP': csts.UC_ARM_REG_SP,
            'SB': csts.UC_ARM_REG_SB, 'LR': csts.UC_ARM_REG_LR,
        }
        self.pc_reg_name = "PC"
        self.pc_reg_value = csts.UC_ARM_REG_PC
        super(UcWrapCPU_arml, self).__init__(*args, **kwargs)
github SimonTheCoder / pyGDB_remote / unicorn_machine.py View on Github external
if __DEBUG__:
            #map a test area
            self.mu.mem_map(0xfffff000, 4*1024)
        self.uc_gen_regs = [
        unicorn.arm_const.UC_ARM_REG_R0,
        unicorn.arm_const.UC_ARM_REG_R1,
        unicorn.arm_const.UC_ARM_REG_R2,
        unicorn.arm_const.UC_ARM_REG_R3,
        unicorn.arm_const.UC_ARM_REG_R4,
        unicorn.arm_const.UC_ARM_REG_R5,
        unicorn.arm_const.UC_ARM_REG_R6,
        unicorn.arm_const.UC_ARM_REG_R7,
        unicorn.arm_const.UC_ARM_REG_R8,
        unicorn.arm_const.UC_ARM_REG_R9,
        unicorn.arm_const.UC_ARM_REG_R10,
        unicorn.arm_const.UC_ARM_REG_R11,
        unicorn.arm_const.UC_ARM_REG_R12,
        unicorn.arm_const.UC_ARM_REG_R13,
        unicorn.arm_const.UC_ARM_REG_R14,
        unicorn.arm_const.UC_ARM_REG_R15
        ]

        self.uc_nzcv_reg = unicorn.arm_const.UC_ARM_REG_CPSR
        self.uc_pc_reg = unicorn.arm_const.UC_ARM_REG_R15

unicorn

Unicorn CPU emulator engine

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GPL-2.0
Latest version published 2 months ago

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