How to use the dace.SDFG function in dace

transient=True,
        storage=dace.dtypes.StorageType.FPGA_Global)

    out_device = copy_out_state.add_read("out_device")

    parent_sdfg.add_array("out_data", [N], dtype=dace.float32)
    out_host = copy_out_state.add_write("out_data")

    copy_out_state.add_edge(out_device, None, out_host, None,
                            dace.memlet.Memlet.simple(out_host, "0:N"))

    ###########################################################################
    # FPGA: make fpga state, which will have two nested sdfg

    ##### AXPY 1 (A+B) part ######
    nested_axpy_1_sdfg = dace.SDFG('compute_axpy_1')
    nested_axpy_1_state = nested_axpy_1_sdfg.add_state("nested_axpy_1_state")

    nested_axpy_1_sdfg.add_array("mem_A", shape=[N], dtype=dace.float32, storage=dace.dtypes.StorageType.FPGA_Global)
    in_read_A = nested_axpy_1_state.add_read("mem_A")
    nested_axpy_1_sdfg.add_array("mem_B", shape=[N], dtype=dace.float32, storage=dace.dtypes.StorageType.FPGA_Global)
    in_read_B = nested_axpy_1_state.add_read("mem_B")
    nested_axpy_1_sdfg.add_stream('stream_out', dtype=dace.float32, storage=dace.dtypes.StorageType.FPGA_Remote)
    stream_write = nested_axpy_1_state.add_write("stream_out")

    tasklet, map_entry, map_exit = nested_axpy_1_state.add_mapped_tasklet(
        'read',  # name
        dict(i='0:N'),  # map range
        dict(inp_A=dace.Memlet.simple(in_read_A.data, 'i'),  # input memlets
             inp_B=dace.Memlet.simple(in_read_B.data, 'i')),
        '''                                                 # code
out = inp_A + inp_B

def make_sdfg(name="transpose"):

    n = dace.symbol("N")
    m = dace.symbol("M")

    sdfg = dace.SDFG(name)

    pre_state = sdfg.add_state(name + "_pre")
    state = sdfg.add_state(name)
    post_state = sdfg.add_state(name + "_post")
    sdfg.add_edge(pre_state, state, dace.InterstateEdge())
    sdfg.add_edge(state, post_state, dace.InterstateEdge())

    _, desc_input_host = sdfg.add_array("a_input", (n, m), dace.float64)
    _, desc_output_host = sdfg.add_array("a_output", (m, n), dace.float64)
    desc_input_device = copy.copy(desc_input_host)
    desc_input_device.storage = dace.StorageType.FPGA_Global
    desc_input_device.location["bank"] = 0
    desc_input_device.transient = True
    desc_output_device = copy.copy(desc_output_host)
    desc_output_device.storage = dace.StorageType.FPGA_Global
    desc_output_device.location["bank"] = 1

in_read_B, None,
        map_entry, None,
        memlet=dace.Memlet.simple(in_read_B.data, '0:N'))

    # Add output path (exit->dst)
    nested_axpy_1_state.add_edge(
        map_exit, None,
        stream_write, None,
        memlet=dace.Memlet.simple(stream_write.data, '0:N'))

    nested_axpy_1_sdfg.fill_scope_connectors()
    nested_axpy_1_sdfg.validate()

    ####### SAVE TO MEMORY ############
    #
    store_sdfg = dace.SDFG('store')
    store_state = store_sdfg.add_state("store_state")
    store_sdfg.add_stream("stream_in", dtype=dace.float32, storage=dace.dtypes.StorageType.FPGA_Remote)
    stream_read = store_state.add_read("stream_in")

    store_sdfg.add_array("mem", shape=[N], dtype=dace.float32,
                                 storage=dace.dtypes.StorageType.FPGA_Global)
    out_write = store_state.add_write("mem")

    store_state.add_edge(
        stream_read, None,
        out_write, None,
        memlet=dace.Memlet.simple(stream_read.data, '0:N'))

    store_sdfg.fill_scope_connectors()
    store_sdfg.validate()

import dace
import dace.graph.labeling
import sys
import time

print(time.time(), 'loading')
a = dace.SDFG.from_file(sys.argv[1])
print(time.time(), 'propagating')
dace.graph.labeling.propagate_labels_sdfg(a)
print(time.time(), 'drawing')
a.draw_to_file()
exit()

a.apply_strict_transformations()

a.apply_strict_transformations()

a.draw_to_file()

def make_read_B_sdfg():

    sdfg = dace.SDFG("gemm_read_B")

    n_begin = sdfg.add_state("n_begin")
    n_entry = sdfg.add_state("n_entry")
    n_end = sdfg.add_state("n_end")

    k_begin = sdfg.add_state("k_begin")
    k_entry = sdfg.add_state("k_entry")
    k_end = sdfg.add_state("k_end")

    m_begin = sdfg.add_state("m_begin")
    m_entry = sdfg.add_state("m_entry")
    m_end = sdfg.add_state("m_end")

    loop_body = sdfg.add_state("read_memory")

    sdfg.add_edge(n_begin, n_entry,

def make_sdfg(specialize):

    if not specialize:
        sdfg = dace.SDFG("filter_fpga")
    else:
        sdfg = dace.SDFG("filter_fpga_{}".format(N.get()))

    sdfg.add_array("A_device", [N],
                   dtype=dace.float32,
                   transient=True,
                   storage=dace.dtypes.StorageType.FPGA_Global)
    sdfg.add_array("A", [N], dtype=dace.float32)

    sdfg.add_array("B_device", [N],
                   dtype=dace.float32,
                   transient=True,
                   storage=dace.dtypes.StorageType.FPGA_Global)
    sdfg.add_array("outsize_device", [1],
                   dtype=dace.uint32,
                   transient=True,

raise SyntaxError('Matrix sizes must match')
        if bopt:
            shape_c = (bopt['b'], shape_a[-2], shape_b[-1])
        else:
            shape_c = (shape_a[-2], shape_b[-1])

        dtype_a = outer_array_a.dtype.type
        dtype_b = outer_array_b.dtype.type
        dtype_c = cdesc.dtype.type

        if outer_array_a.storage != outer_array_b.storage:
            raise ValueError("Input matrices must have same storage")
        storage = outer_array_a.storage

        # Create replacement SDFG
        sdfg = dace.SDFG(node.label + "_sdfg")

        _, array_a = sdfg.add_array("_a",
                                    shape_a,
                                    dtype_a,
                                    strides=strides_a,
                                    storage=storage)
        _, array_b = sdfg.add_array("_b",
                                    shape_b,
                                    dtype_b,
                                    strides=strides_b,
                                    storage=storage)
        _, array_c = sdfg.add_array("_c",
                                    shape_c,
                                    dtype_c,
                                    strides=cdata[-1],
                                    storage=storage)

def make_sdfg(specialize):

    if not specialize:
        sdfg = dace.SDFG("filter_fpga")
    else:
        sdfg = dace.SDFG("filter_fpga_{}".format(N.get()))

    sdfg.add_array("A_device", [N],
                   dtype=dace.float32,
                   transient=True,
                   storage=dace.dtypes.StorageType.FPGA_Global)
    sdfg.add_array("A", [N], dtype=dace.float32)

    sdfg.add_array("B_device", [N],
                   dtype=dace.float32,
                   transient=True,
                   storage=dace.dtypes.StorageType.FPGA_Global)
    sdfg.add_array("outsize_device", [1],
                   dtype=dace.uint32,
                   transient=True,
                   storage=dace.dtypes.StorageType.FPGA_Global)
    sdfg.add_array("B", [N], dtype=dace.float32)

def make_nested_sdfg(parent):

    sdfg = dace.SDFG("spmv_inner")

    set_zero_state = sdfg.add_state("set_zero")
    set_zero_b = set_zero_state.add_scalar(
        "b_buffer",
        dtype,
        transient=True,
        storage=dace.dtypes.StorageType.FPGA_Registers)
    set_zero_tasklet = set_zero_state.add_tasklet("set_zero", {}, {"b_out"},
                                                  "b_out = 0")
    set_zero_state.add_memlet_path(set_zero_tasklet,
                                   set_zero_b,
                                   src_conn="b_out",
                                   memlet=dace.memlet.Memlet.simple(
                                       set_zero_b, "0"))

    write_back_state = sdfg.add_state("write_back")

def make_read_A_sdfg():

    sdfg = dace.SDFG("gemm_read_A")

    n_begin = sdfg.add_state("n_begin")
    n_entry = sdfg.add_state("n_entry")
    n_end = sdfg.add_state("n_end")

    k_begin = sdfg.add_state("k_begin")
    k_entry = sdfg.add_state("k_entry")
    k_end = sdfg.add_state("k_end")

    loop_body = sdfg.add_state("read_memory")

    sdfg.add_edge(n_begin, n_entry,
                  dace.sdfg.InterstateEdge(assignments={"n": 0}))
    sdfg.add_edge(k_begin, k_entry,
                  dace.sdfg.InterstateEdge(assignments={"k": 0}))