How to use the pyvex.const.get_type_size function in pyvex

def SimIRExpr_Load(engine, state, expr):
    # size of the load
    size_bits = get_type_size(expr.type)
    size = size_bits // state.arch.byte_width

    # get the address expression and track stuff
    with state.history.subscribe_actions() as addr_actions:
        addr = engine.handle_expression(state, expr.addr)

    if o.UNINITIALIZED_ACCESS_AWARENESS in state.options:
        if getattr(addr._model_vsa, 'uninitialized', False):
            raise SimUninitializedAccessError('addr', addr)

    if o.DO_LOADS not in state.options:
        # only do the load if, uh, we have to
        result = state.solver.Unconstrained("load_expr_%#x_%d" % (state.scratch.ins_addr, state.scratch.stmt_idx), size_bits)
    else:
        # load from memory and fix endianness
        result = state.memory.load(addr, size, endness=expr.endness)

def size_bits(self, ty=None):
        if not ty:
            if self.type is not None:
                return get_type_size(self.type)
            return len(self.stmt)
        else:
            # Allow subclasses to define which parameter they consider their size
            return get_type_size(ty)

def size_bits(self, ty=None):
        if not ty:
            if self.type is not None:
                return get_type_size(self.type)
            return len(self.stmt)
        else:
            # Allow subclasses to define which parameter they consider their size
            return get_type_size(ty)

def size_bits(self, ty=None):
        if not ty:
            if self.type is not None:
                return get_type_size(self.type)
            return len(self.stmt)
        else:
            # Allow subclasses to define which parameter they consider their size
            return get_type_size(ty)

def translate_irconst(state, c):
    size = get_type_size(c.type)
    if isinstance(c.value, int):
        return state.solver.BVV(c.value, size)
    elif isinstance(c.value, float):
        if o.SUPPORT_FLOATING_POINT not in state.options:
            raise UnsupportedIRExprError("floating point support disabled")
        if size == 32:
            return state.solver.FPV(c.value, FSORT_FLOAT)
        elif size == 64:
            return state.solver.FPV(c.value, FSORT_DOUBLE)
        else:
            raise SimExpressionError("Unsupported floating point size: %d" % size)
    raise SimExpressionError("Unsupported constant type: %s" % type(c.value))

def size_bits(self, ty=None):
        if not ty:
            if self.type is not None:
                return get_type_size(self.type)
            return len(self.expr)
        else:
            # Allow subclasses to define which parameter they consider their size
            return get_type_size(ty)

action_objects = []
            for arg, ex in zip(expr.args, exprs):
                if isinstance(arg, RdTmp):
                    action_objects.append(SimActionObject(ex, tmp_deps=frozenset({arg.tmp})))
                elif isinstance(arg, Get):
                    action_objects.append(SimActionObject(ex, reg_deps=frozenset({arg.offset})))
                else:
                    action_objects.append(SimActionObject(ex))
            r = SimActionOperation(state, expr.op, action_objects, result)
            state.history.add_action(r)

    except UnsupportedIROpError:
        if o.BYPASS_UNSUPPORTED_IROP in state.options:
            state.history.add_event('resilience', resilience_type='irop', op=expr.op, message='unsupported IROp')
            res_type = get_op_retty(expr.op)
            res_size = get_type_size(res_type)
            if o.UNSUPPORTED_BYPASS_ZERO_DEFAULT in state.options:
                result = state.solver.BVV(0, res_size)
            else:
                result = state.solver.Unconstrained(type(expr).__name__, res_size)
            if res_type.startswith('Ity_F'):
                result = result.raw_to_fp()
        else:
            raise
    except SimOperationError as e:
        e.bbl_addr = state.scratch.bbl_addr
        e.stmt_idx = state.scratch.stmt_idx
        e.ins_addr = state.scratch.ins_addr
        e.executed_instruction_count = state.history.recent_instruction_count
        raise

    return result

self._vector_type = None
        self._vector_zero = None
        self._vector_count = None

        self._rounding_mode = None

        for k,v in self.op_attrs.items():
            if v is not None and ('size' in k or 'count' in k):
                v = int(v)
            setattr(self, '_%s'%k, v)

        # determine the output size
        #pylint:disable=no-member
        self._output_type = pyvex.get_op_retty(name)
        #pylint:enable=no-member
        self._output_size_bits = pyvex.const.get_type_size(self._output_type)

        size_check = self._to_size is None or (self._to_size*2 if self._generic_name == 'DivMod' else self._to_size) == self._output_size_bits
        if not size_check:
            raise SimOperationError("VEX output size doesn't match detected output size")


        #
        # Some categorization
        #

        generic_names.add(self._generic_name)
        if self._conversion is not None:
            conversions[(self._from_type, self._from_signed, self._to_type, self._to_signed)].append(self)

        if len({self._vector_type, self._from_type, self._to_type} & {'F', 'D'}) != 0:
            self._float = True

def size_bits(self, ty=None):
        if not ty:
            if self.type is not None:
                return get_type_size(self.type)
            return len(self.expr)
        else:
            # Allow subclasses to define which parameter they consider their size
            return get_type_size(ty)