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path, file_ = os.path.split( source_elf )
dest_elf = file_+'-new'
mem_image = None
with open(source_elf,'rb') as file_obj:
mem_image = elf.elf_reader( file_obj )
# Add a bootstrap section at address 0x400
bootstrap_asm = """
lui r29, 0x0007
ori r29, r0, 0xfffc
j 0x1000
"""
bootstrap_mem_image = pisa_encoding.assemble( bootstrap_asm )
bootstrap_bytes = bootstrap_mem_image.get_section(".text").data
mem_image.add_section( ".bootstrap", 0x400, bootstrap_bytes )
import struct
print len( bootstrap_bytes )
for i in [0, 4, 8]:
print '{:08x}'.format( struct.unpack('
import sys
import os
sys.path.append('/Users/dmlockhart/vc/git-brg/parc/pymtl')
import pisa.elf as elf
import pisa.pisa_encoding as pisa_encoding
# Load the elf file
source_elf = sys.argv[1]
path, file_ = os.path.split( source_elf )
dest_elf = file_+'-new'
mem_image = None
with open(source_elf,'rb') as file_obj:
mem_image = elf.elf_reader( file_obj )
# Add a bootstrap section at address 0x400
bootstrap_asm = """
lui r29, 0x0007
ori r29, r0, 0xfffc
j 0x1000
"""
bootstrap_mem_image = pisa_encoding.assemble( bootstrap_asm )
bootstrap_bytes = bootstrap_mem_image.get_section(".text").data
mem_image.add_section( ".bootstrap", 0x400, bootstrap_bytes )
import struct
print len( bootstrap_bytes )
for i in [0, 4, 8]:
try:
# Update instruction counts
s.num_total_inst += 1
if s.isa.stats_en:
s.num_inst += 1
# Set trace string in case the fetch yields
s.trace = " "*29
# Fetch instruction
s.pc = s.isa.PC.uint()
s.inst = PisaInst( s.imem[ s.pc : s.pc+4 ] )
# Set trace string in case the execution function yeilds
s.trace = "#".ljust(29)
# Execute instruction
s.isa.execute( s.inst )
# Ensure that the stats_en and status ports are current
if not s.test_en:
s.stats_en.next = s.isa.stats_en
s.status.next = s.isa.status
# Trace instruction
if s.ifetch_wait > 0:
s.trace_X = "~w{}".format(s.ifetch_wait).ljust(29)
if not s.imemresp_q.empty():
inst = PisaInst(s.imemresp_q.first())
s.ifetch_wait -= 1
s.trace_X = "~w{}".format(s.ifetch_wait).ljust(29)
s.imemresp_q.deq()
elif not s.pc_queue_FX.empty() \
and not s.imemresp_q.empty() \
and not s.inst_queue_XW.full() \
and not s.wb_queue_XW.full():
s.stall_X = False
inst = PisaInst(s.imemresp_q.first())
s.execute_dispatch[inst.name]( s, inst )
if not s.stall_X:
if not s.pc_queue_FX.empty():
s.pc_queue_FX.deq()
s.imemresp_q.deq()
s.inst_queue_XW.enq( inst )
s.trace_X = str(inst).ljust(29)
else:
s.trace_X = ( "#" + s.stall_type_X ).ljust(29)
# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
# F: Fetch Pipeline Stage
# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
s.trace_F = " ".ljust(8)
if not s.stall_W:
s.inst_queue_XW.deq()
s.wb_queue_XW.deq()
# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
# X: Execute Pipeline Stage
# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
s.trace_X = " "*29
if s.ifetch_wait > 0:
s.trace_X = "~w{}".format(s.ifetch_wait).ljust(29)
if not s.imemresp_q.empty():
inst = PisaInst(s.imemresp_q.first())
s.ifetch_wait -= 1
s.trace_X = "~w{}".format(s.ifetch_wait).ljust(29)
s.imemresp_q.deq()
elif not s.pc_queue_FX.empty() \
and not s.imemresp_q.empty() \
and not s.inst_queue_XW.full() \
and not s.wb_queue_XW.full():
s.stall_X = False
inst = PisaInst(s.imemresp_q.first())
s.execute_dispatch[inst.name]( s, inst )
if not s.stall_X:
if not s.pc_queue_FX.empty():
s.pc_queue_FX.deq()
def execute_mfc0( s, inst ):
# CP0 register: mngr2proc
if inst.rd == 1:
bits = s.mngr2proc_queue.popleft()
s.mngr2proc_str = str(bits)
s.R[inst.rt] = bits
# CPO register: coreid
elif inst.rd == 17:
s.R[inst.rt] = 0
else:
raise PisaSemantics.IllegalInstruction(
"Unrecognized CPO register ({}) for mfc0 at PC={}" \
.format(inst.rd.uint(),s.PC) )
s.PC += 4
# CP0 register: status
if inst.rd == 1:
s.status = s.R[inst.rt]
# CP0 register: proc2mngr
elif inst.rd == 2:
bits = s.R[inst.rt]
s.proc2mngr_str = str(bits)
s.proc2mngr_queue.append( bits )
# CPO register: stats_en
elif inst.rd == 10:
s.stats_en = bool(s.R[inst.rt])
else:
raise PisaSemantics.IllegalInstruction(
"Unrecognized CPO register ({}) for mtc0 at PC={}" \
.format(inst.rd.uint(),s.PC) )
s.PC += 4
def add_section( self, section, addr=None, data=None ):
if isinstance( section, SparseMemoryImage.Section ):
self.sections.append( section )
else:
sec = SparseMemoryImage.Section( section, addr, data )
self.sections.append( sec )
def add_section( self, section, addr=None, data=None ):
if isinstance( section, SparseMemoryImage.Section ):
self.sections.append( section )
else:
sec = SparseMemoryImage.Section( section, addr, data )
self.sections.append( sec )
import struct
print len( bootstrap_bytes )
for i in [0, 4, 8]:
print '{:08x}'.format( struct.unpack('