Fix ART internals parsing for 32-bit ARM

Code generation was using the wrong register name.

Author: oleavr

lib/android.js

@@ -1917,11 +1917,11 @@ function recompileExceptionClearForArm (buffer, pc, exceptionClearImpl, nextFunc
             const clobberedRegs = ['r0', 'r1', 'r2', 'r3', nzcvqReg, 'r9', 'r12', 'lr'];
 
             writer.putPushRegs(clobberedRegs);
-            writer.putMrsRegReg(nzcvqReg, 'apsr_nzcvq');
+            writer.putMrsRegReg(nzcvqReg, 'apsr-nzcvq');
 
             writer.putCallAddressWithArguments(callback, [ threadReg ]);
 
-            writer.putMsrRegReg('apsr_nzcvq', nzcvqReg);
+            writer.putMsrRegReg('apsr-nzcvq', nzcvqReg);
             writer.putPopRegs(clobberedRegs);
 
             foundCore = true;